PLL Phase Detector / Comparator

- a phase detector or phase comparator used within a PLL phase locked loop produces an error voltage between the reference signal and VCO to keep the VCO on the required frequency.

The phase detector is the core element of a phase locked loop, PLL. Its action enables the phase differences in the loop to be detected and the resultant error voltage to be produced.

There is a variety of different circuits that can be used as phase detectors, some that use what may be considered as analogue techniques, while others use digital circuitry. However the most important difference is whether the phase detector is sensitive to just phase or whether it is sensitive to frequency and to phase. Thus phase detectors may be split into two categories:

  • Phase only sensitive detectors
  • Phase / frequency detectors

Phase only sensitive detectors

Phase detectors that are only sensitive to phase are the most straightforward form of detector. They simply produce an output that is proportional to the phase difference between the two signals. When the phase difference between the two incoming signals is steady, they produce a constant voltage. When there is a frequency difference between the two signals, they produce a varying voltage.

The difference frequency product is the one used to give the phase difference. It is quite possible that the difference frequency signal will fall outside the pass-band of the loop filter. If this occurs then no error voltage will be fed back to the Voltage Controlled Oscillator (VCO) to bring it into lock. This means that there is a limited range over which the loop can be brought into lock, and this is called the capture range. Once in lock the loop can generally be pulled over a much wider frequency band.

To overcome this problem the oscillator must be steered close to the reference oscillator frequency. This can be achieved in a number of ways. One is to reduce the tuning range of the oscillator so that the difference product will always fall within the pass-band of the loop filter. In other instances another tune voltage can be combined with the feedback from the loop to ensure that the oscillator is in the correct region. This is approach is often adopted in microprocessor systems where the correct voltage can be calculated for any given circumstance.

There are several forms of phase detector that can be used. These fall into the following categories:

  • Diode ring mixer phase detector:   This is the simplest form of phase detector and it can be synthesised from a diode ring mixer. The diode ring phase detector is a simple and effective form of phase detector that can be implemented using a standard diode ring module.

    A diode ring, or double balanced mixer can be used as a phase detector
    Diode ring phase detector


    The mathematics shows that the voltage at the IF port of the diode ring mixer varies as the cosine of the phase different between the inputs ta the RF and LO inputs to the diode ring. This means that null or 0V readings are obtained for a zero degree phase difference, but also at odd multiples of Π/2. Maximum and minimum voltages are seen at points where the phase difference is a multiple of Π.

    The cosine response curve of a diode ring phase detector
    Diode ring phase detector response curve
  • XOR circuit:   The exclusive OR, XOR phase detector circuit can provide a very useful simple phase detector for some applications.

    An exclusive OR circuit can be used to provide phase detection
    Exclusive OR phase detector


    The way in which an exclusive OR, XOR phase detector works can be seen by the diagram below:

    The waveforms showing how an exclusive OR phase detector operates
    XOR phase detector waveforms


    It can be seen that using these waveforms, the XOR gate can be used as a simple but effective phase detector.

    As might be expected for such a simple circuit, there are a few drawbacks to using an XOR phase detector:

    • The phase detector is sensitive to the clock duty cycle. This means that a steady duty cycle, i.e. 1:1 should be used. It will lock with a phase error if the input duty cycles are not 50%.
    • The output characteristic of the XOR PD show repetitions and gain changes. This means that if there is a frequency difference between the input reference and PLL feedback signals the phase detector can jump between regions of different gain. The characteristic of the phase detector is as shown below:

      The response curve of this PD shows repetitions and gain changes.
      XOR phase detector response curve
    • The nominal lock point with an XOR phase detector is also at the 90° static phase shift point.
    Unlike an analogue mixer phase detector, the XOR version is independent of input amplitude and constant over a Π phase range.

Phase-frequency detectors

Another form of detector is said to be phase-frequency sensitive. These circuits have the advantage that whilst the phase difference is between ± 180° a voltage proportional to the phase difference is given. Beyond this the circuit limits at one of the extremes. In this way no AC component is produced when the loop is out of lock and the output from the phase detector can pass through the filter to bring the phase locked loop, PLL, into lock.

There is a number of different types of phase-frequency detectors that are available.

  • Edge triggered JK flip flop phase frequency detector:   This form of phase comparator is used in some designs.

    The basic JK Flip-Flop
    JK Flip Flop


    The idea behind the JK flip flop based comparator is that it is a sequentially based circuit and this can be used to provide two signals: one to charge, and one to discharge a capacitor.

    Often when using this form of phase detector, an active charge pump is recommended.


    JK Flip Flop States
    v1 v2 Qn+1
    0 0 Qn
    0 1 0
    1 0 1
    1 1 Qn bar


    The waveforms that are generated by the JK flip flop with two input signals.
    JK Flip Flop phase detector waveforms


    These waveforms can be interpreted and it is found that the overall response appears as below.

    The response curve of this PD shows repetitions.
    JK flip flop phase detector response
  • Dual D type phase comparator:   This type of phase frequency detector uses two D type flip flops and an NAND gate, although there are a number of slightly different variants. This type of phase comparator is possibly the most widely used form of detector because of its performance and ease of design and use.

    The circuit for the dual D-type comparator uses the two D-type flip flops with the reference and VCO signals being compared entering the clock inputs, one on each D-type. The NAND gate output is fed to the reset, R, inputs of both D-types. The inputs to the NAND gate are taken from the Q outputs and the output to the loop filter being taken from one of the Q outputs.

    A dual D-type phase detector circuit is often also called the tri-state phase detector
    Dual D-Type phase detector circuit


    Obviously various configurations using Q outputs, Q-bar outputs and AND gates are possible, but for simplicity sake the version using the Q outputs from the D-types and using a NAND gate is shown.

Phase detector dead zone

One of the issues that faces the designers of very low phase noise synthesizers and phase locked loops, is a phenomenon referred to as the phase detector dead zone.

This occurs where digital phase detectors are used. It is found that when the loop is in lock and there is a small phase difference between the two signals, very short pulses are created by the phase detector logic gates. Being very short, these pulses may not propagate and add charge into the charge pump / loop filter. As a result the loop gain is reduced and this forces up the loop jitter / phase noise.

The curve or characteristic of a phase detector that exhibits a dead zone
Phase detector output characteristic
showing dead zone

To overcome this one solution is to add a delay in the phase detector reset path, i.e. on the output of the NAND gate in the dual D-type detector before the reset terminals of the D-types. This forces a minimum pulse length.

By Ian Poole


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