15 Sep 2017
Conformal Smart Logic Equivalence Checker unveiled
Cadence Design Systems has announced the Cadence Conformal Smart Logic Equivalence Checker (LEC), the next-generation equivalence checking solution that delivers a significant improvement in equivalence checking runtime with minimal user effort.
The Conformal Smart LEC delivers an average of 4X runtime improvement compared to the previous generation of logic equivalency checking tools with the same compute resources.
With rapidly growing chip functionality, design sizes are increasing. In addition, with the latest advances in logic synthesis at advanced nodes, designers employ aggressive synthesis techniques to achieve power, performance and area (PPA) goals. These advances in both design size and complexity stress equivalence checking proof methods and can result in long runtimes and sometimes inconclusive results. Equivalence checking is a critical step in digital tapeout flows, and the Conformal Smart LEC solution addresses these issues. The key technology components of the Conformal Smart LEC are:
Massively parallel architecture automatically partitions designs and distributes formal proof strategies across multiple machines and CPUs, and can scale seamlessly to 100s of CPUs for improved runtime. This process is fully transparent to the user and does not require manual configurations.
Adaptive proof technology finds the fastest solution to a conclusive proof with minimal user effort. It analyzes each partition and determines the optimal formal algorithm to use to minimize runtime and avoid proof timeouts—especially on designs with complex behavioral datapath components.
“We’ve already seen several customers achieve significant runtime improvements and aggressive PPA goals with the Cadence Conformal Smart LEC,” said Dr. Anirudh Devgan, executive vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “Additionally, our massively parallel architecture and adaptive proof technologies for equivalence checking reduce the need for manual tasks so customers can deliver complex designs to market faster.”
“For complicated designs including deep logic cones, it often used to take multiple expert user iterations per block to prove RTL-to-gate logic equivalence,” said Hideyuki Okabe, senior manager, Digital Design Technology Department, Shared R&D Division 2, Broad-Based Solution Business Unit at Renesas Electronics Corporation. “The Cadence Conformal Smart LEC automatically identifies the right proof strategy and has reduced these iterations to just one. Also, the Conformal Smart LEC’s massively parallel architecture has enabled us to reduce our average runtime by 4X. With our designs moving to smaller process nodes and continuing to grow in size and complexity, this technology is crucial to meet our current and future time-to-market goals.”
The new Conformal Smart LEC further extends the innovation within the Cadence digital design and signoff suite and supports the company’s broader System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.
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