21 Nov 2018
Cadence announces tapeout of GDDR6 IP on Samsung’s 7LPP process
Cadence Design Systems has announced the tapeout of a complete GDDR6 memory IP solution on Samsung’s 7LPP process. GDDR6 memory is targeted at very high-bandwidth applications including machine learning, AI, cryptocurrency mining, graphics, automated driving, ADAS and high-performance computing (HPC).
The Cadence GDDR6 IP solution consists of PHY, controller and Verification IP (VIP). Samsung is enabling this advanced IP on the 7LPP foundry process for customers to design next-generation chips in the hottest application areas, for use with high-performance GDDR6 memory products.
Until now, GDDR memories have been predominantly used for graphics applications, with limited use elsewhere. As a result, DDR4 and LPDDR4 have been the memories of choice for early adopters addressing high-bandwidth memory applications. GDDR6 offers 5X faster memory bandwidth than the fastest speed of DDR4 at a moderate cost, making it ideal for such applications. However, design at GDDR6 data rates requires new architecture and techniques, which has limited the adoption of GDDR technology in non-graphics applications in the past. Samsung and Cadence are poised to address this market need with robust GDDR6 solutions that include the Cadence Denali DDR controller and silicon-proven high-speed SerDes technology.
The new GDDR6 IP allows up to 16Gb/sec bandwidth per pin, or over 500Gb/sec peak bandwidth between the SoC and each GDDR6 memory die. This enables users to design high-memory-bandwidth GDDR6 interfaces with a lower number of DRAM dies than is possible with DDR4, reducing both PCB area and packaging pins. Cadence’s unique, single-vendor GDDR6 IP solution speeds integration and reduces interoperability risk. In addition, customers benefit from reduced risk of interoperability issues between their SoC and memory devices because the GDDR6 IP was developed in close collaboration with Samsung. Cadence VIP rounds out the complete IP offering, with the Cadence GDDR6 Memory Model delivering the advanced checks, coverage, verification planning and modeling flexibility required to mitigate memory silicon escapes using the Cadence Verification Suite.
Additional Features/Benefits of the Cadence GDDR6 IP:
Cadence design techniques reuse technology from Cadence’s silicon-proven DDR and SerDes designs, resulting in lower risk when implementing GDDR6
Low bit-error rate (BER) reduces retries on the memory bus, providing greater bandwidth and lower maximum latency
Cadence’s wide design margin allows users to implement GDDR6 on PCBs with common materials such as FR4, reducing the cost of GDDR6 deployment
Cadence’s GDDR6 reference design allows users to replicate Cadence’s test chip results in their own products
Cadence’s VIP, now extended with GDDR6 support, enabled robust verification of the GDDR6 interface
“GDDR6 IP is necessary for broader adoption in graphics, AI, machine learning, HPC and other applications requiring very high-memory bandwidth,” said Jaehong Park, senior vice president of Foundry Design Service Team at Samsung Electronics. “Cadence’s tapeout of GDDR6 IP in Samsung Foundry’s 7LPP process is a milestone in our successful collaboration to deliver a superior GDDR6 solution to our mutual customers.”
“Through our collaboration with Samsung and successful GDDR6 IP tapeout, Cadence is well positioned to accelerate market adoption of this vital new technology,” said Amjad Qureshi, corporate vice president, R&D, Design IP at Cadence. “Our complete GDDR6 IP solution leverages industry-leading technology and proven design techniques to both reduce implementation risk and speed time to market. SoC providers can start their next-generation memory designs today with the confidence that Cadence GDDR6 IP is ready for integration.”
Cadence GDDR6 IP and memory models are available now for customer engagements. Design files are ready for select customers to begin integration work with confidence that the Cadence GDDR6 IP will work as intended in its application.
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