03 Dec 2015
Virtuoso advanced-node platform improves designer productivity
Cadence Design Systems has announced the delivery of the new Virtuoso Advanced-Node Platform that is enabled for all advanced 10nm FinFET designs.
This next-generation custom design platform delivers up to 5X improvement in designer productivity and also provides initial support for emerging 7nm technologies.
To address the challenges that come with advanced-node FinFET designs, innovative capabilities in the Cadence Virtuoso Advanced-Node Platform allow designers to better manage complexity and process effects. The key capabilities include:
Multi-patterning and color-aware layout: Supports more than four multi-patterned layers for design decomposition, enabling users to be far more productive through access to a variety of coloring options
Electrically aware design (EAD): Allows designers to address parasitic and electro-migration (EM) effects during the design cycle versus waiting until designs are completed, thereby reducing design cycles times by up to 30 percent
Module generator (ModGen)-based device array flow: Provides support for in-array routing, greatly reducing design iterations and improving designer productivity by up to 25X
10nm custom routing: Supports new design rules, greatly simplifies layout creation and minimizes coloring errors that can be pervasive when designing on the 10nm process
In-design physical verification system (iPVS): Enables layout engineers to instantaneously detect and fix errors as designs are being implemented, which can reduce design rule errors while improving overall designer productivity by up to 15 percent
"Innovation is the core of our business, and through our close collaboration with leading foundries and customers, weve been able to optimize our custom design platform for advanced-node processes", said Tom Beckley, senior vice president and general manager, Custom IC and PCB Group at Cadence. "The new features included with the Virtuoso Advanced-Node Platform can enable our customers to achieve the best possible results, and we already have several customers using it in production design starts to reduce the overhead inherent with 10nm designs."
Most popular news in Circuit DesignMarvell opens CISPR25 automotive EMC laboratory
Firefighting robots create 3D thermal images for rescuers
LabVIEW 2015 provides faster coding & operation
RS and Allied ship 512MB Raspberry Pi boards
Affordable PCB design tools introduced
Share this page
Want more like this? Register for our newsletter