02 Feb 2015

Latest SMBus specification addresses demands of emerging technologies

The System Management Interface Forum (SMIF Inc.) has announced the latest version of its System Management Bus (SMBus) specification. Version 3.0 is backwards compatible and incorporates a number of major revisions to ease implementation for users of the protocol, significantly broaden performance capabilities to ensure compatibility with the latest topologies and harmonize the specification with the I2C and Power Management Bus (PMBus) specifications.

The SMBus is a two-wire interface through which system component chips and devices can communicate with each other and with the rest of the system. SMBus is designed to provide a control bus for system and power management related tasks and may be used instead of individual control lines to pass messages to and from devices.

In addition to reducing pin counts and supporting a flexible and expandable environment, SMBus delivers a useful range of functionality such as saving states from a suspended event and the reporting of errors.

Recognizing the ability of the latest processors and custom logic to work at greater speeds, the 100 kHz bus frequency offered by SMBus 2.0 is complemented with two further speeds of 400 kHz and 1 MHz in the newly announced version 3.0. The addition of these increased speeds has in turn necessitated the adjustment and re-organization of high power electrical drive levels.

A further update has seen the data hold time specification changed to match the I2C specification. The decision to align this parameter recognizes that most devices on the market manage data hold time in accordance with I2C.

Version 3.0 also includes the removal of a specification for minimum immunity to noise on the clock and data lines as the SMIF Working Group found that no supplier of SMBus devices or system OEM using SMBus ever tested against the parameter. Other changes include the re-use of defunct special bus addresses (formerly reserved for ACCESS Bus host and ACCESS Bus default address) for the zone read and write protocols that were introduced in revision 1.3 of the PMBus specification, an increase from 32 to 255 for the maximum number of bytes allowed in the write-block read process call, and the addition of protocols to read 32 and 64 bits of data in a single transaction.

Most popular news in Circuit Design

Marvell opens CISPR25 automotive EMC laboratory
Firefighting robots create 3D thermal images for rescuers
LabVIEW 2015 provides faster coding & operation
RS and Allied ship 512MB Raspberry Pi boards
Affordable PCB design tools introduced

All news in this channel | All news


Share this page


Want more like this? Register for our newsletter






Securing the future of IoT | Rutronik
Securing the future of IoT
Co-authored by Bernd Hantsche, Head of the GDPR Team of Excellence and Marketing Director Embedded & Wireless and Richard Ward, ‎Semiconductor Marketing Manager at Rutronik.









Radio-Electronics.com is operated and owned by Adrio Communications Ltd and edited by Ian Poole. All information is © Adrio Communications Ltd and may not be copied except for individual personal use. This includes copying material in whatever form into website pages. While every effort is made to ensure the accuracy of the information on Radio-Electronics.com, no liability is accepted for any consequences of using it. This site uses cookies. By using this site, these terms including the use of cookies are accepted. More explanation can be found in our Privacy Policy