FRAM Ferroelectric RAM Technology & Operation

- Ferroelectric RAM technology is based around the use of crystals of a dielectric that have a reversible electric polarisation.

Despite the name, ferroelectric RAM technology does not use the properties of ferrous materials. Instead it uses the properties crystals of a dielectric that have a reversible electric polarisation.

FRAM technology has all the advantages of being a non-volatile memory along with an almost unlimited number of read-write cycles. It also offers a very low level of power consumption, making it a contender for the memory for many applications.

Although the technology is less dense than other more established technologies, and has a higher cost, these issues are being addressed as development progresses.

Basics of FRAM - ferroelectric effect

As the name of the memory implies, the ferroelectric RAM technology depends upon the ferroelectric effect for its operation.

This property is observed in a group of materials known as Perovskites. These materials have a crystalline structure with an atom at the centre. This atom has two equal and stable low energy states and these determine the position of the atom.

This is a variety of different compounds that fall into this category. These include substances including: Lead Zirconate Titanate, etc..

If a field is applied to the crystal in the required plane, then the atom will move in the direction of the field. It is the position of the atom that then acts as the determination of the state of the material and in turn this can be used to store data.

The two states of the ferroelectric material are referred to as 'up polarisation' when the atom is on the top position, and 'down polarisation' when the atom is in the bottom position.

Ferroelectric crystal up polarisation

Ferroelectric crystal down polarisation

Because there is energy required within the transitions, there is a hysteresis loop over which the ferroelectric material operates.

Ferroelectric hysteresis loop

It should be noted that the ferroelectric crystals do not contain any ferrous material. They gain their name from the similarity of the graph of charge plotted as a function of voltage to the familiar BH curve of a magnetic material. In fact ferroelectric materials are switched only by electric fields and they are not affected by magnetic fields.

FRAM operation

It can be seen that there can be two different states within ferroelectric materials. This can be used within a capacitor to create two states for a memory cell.

The capacitor can be polarised either up or down by applying the relevant field.

The ferroelectric capacitor and polarisation as used in a ferroelectric RAM
Ferroelectric capacitor polarisation

The key to the operation of the FRAM is that the capacitance of the ferroelectric capacitor is variable. If the capacitor is not switched when an electric field is applied, i.e. no change in polarisation, then it behaves in the normal linear fashion. However if is switched, then an additional charge is induced and this must have resulted from an increase in capacitance.

To enable this effect to be used in a memory cell an additional active element, a FET is used. The cell has a word line and also a bit line to enable the individual cell to be accessed.

The basic cell of the ferroelectric memory showing the connections to the capacitor and FET.
Basic Ferroelectric memory cell

FRAM read cycle

The read operation of the FRAM memory requires a number of stages. It is very similar to that used within dynamic RAM, DRAM. The bit line voltage is simply compared to a reference. This reference is set between the two levels, i.e. above the un-switched and below the switch voltages. The sense amplifier then acts as a comparator amplifying the difference to give either logic 1 or logic 0.

To look at the sequence more closely, the cell will initially be in its inactive state where the Bit Line is low, Plate Line low and the Word Line is low as shown in 'A'. It then progresses through the memory access sequence.

The basic cell access sequence for a FRAM memory.
Ferroelectric memory cell access sequence

The access operation starts by placing voltages onto the Word Line and Plate Line as defined in 'B'.

There are two cases that need to be considered. By placing a voltage across the capacitor it will either switch, or not switch dependent upon its state.

  • Where capacitor state switches:   These voltages place a field across the ferroelectric capacitor which switches as shown in 'C'.

    This switching process induces a charge which is shared with the Bit Line capacitance represented by Cbit and the switched ferroelectric capacitor, Cs. There is also a small capacitance resulting from the transistor and other interconnection parasitics, but the effect is generally small.

    The resulting voltage on the Bit Line is therefore proportional to the ratio of the capacitances, Cs : Cbit. Hence the voltage on the bit line is Cs / Cbit x Vdd.
  • No switching of capacitor state:   If the capacitor does not switch then there is no additional charge induced.

It can be seen that the data within the cell can be changed in the read operation, i.e. reading an FRAM cell is a destructive process. It therefore requires the cell to be re-written if it was changed.

The FRAM memory operation is designed so that the charge induced in the switched capacitor is at least twice the charge available from the un-switched capacitor. This means that the switched capacitance must be at least twice the un-switched capacitance. It then follows that the Bit Line voltage fort he switched case will be at least twice that of the un-switched case..

This voltage can be sensed using sense amplifiers similar to those used in DRAMs.

Also like DRAMs, FRAMs have a cycle time. This means that the time between successive random accesses is equal to the cycle time and not just the access time.

FRAM write operation

The FRAM operation for writing to memory addresses uses the same basic principles as those employed in the read operation.The control circuitry for the memory applies a field in the required direction across the ferroelectric capacitor to write the desired data.

Once in place the data will remain intact even when the power is removed from the chip. As it requires energy to switch the memory from one state to another, charge does not leak away as in other types of memory including DRAM or even Flash to a small degree, and will remain intact indefinitely.

By Ian Poole

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Securing the future of IoT
Co-authored by Bernd Hantsche, Head of the GDPR Team of Excellence and Marketing Director Embedded & Wireless and Richard Ward, ‎Semiconductor Marketing Manager at Rutronik. is operated and owned by Adrio Communications Ltd and edited by Ian Poole. All information is © Adrio Communications Ltd and may not be copied except for individual personal use. This includes copying material in whatever form into website pages. While every effort is made to ensure the accuracy of the information on, no liability is accepted for any consequences of using it. This site uses cookies. By using this site, these terms including the use of cookies are accepted. More explanation can be found in our Privacy Policy