Flash Memory Wear, Reliability & Life

- overview of Flash memory wear, its reliability and lifetime together with techniques including wear levelling.

One of the issues with flash memory is that it has a finite lifetime and can only support a finite number of programme / write cycles. This process is known as flash memory wear.

It is important to incorporate the flash memory wear and lifetime into any decisions about the use of flash memory.

Also when using flash memory, it is necessary to be aware of the lifetime and wear limitations so that data is not lost.

Flash memory wear basics

Significant improvements have been made in terms of flash memory wear since the first flash devices were introduced. Originally the flash memory lifetime was measured in terms of a few thousand programme- erase cycles.

Today most commercially available flash memory is guaranteed to withstand 100 000 or more programme-erase cycles with some manufacturers guaranteeing a life of over 1 000 000 cycles.

Flash memory wear out mechanism

The flash memory wear out mechanism results from the structure of the device.

A typical device structure is seen below, and from this it can be seen that there are various layers and areas to the device.

Diagram showing the typical strcuture of a Flash memory cell
Flash memory cell structure

The wear-out mechanism for flash devices occurs as a result of usage causing the tunnel oxide layer to degrade. Although there are other mechanism that can cause the device to fail, it is the tunnel oxide layer degradation that causes the flash memory wear issue.

Flash memory uses a process called channel hot-electron injection for programming each cell and Fowler-Nordheim tunnelling for the erase cycle. However it is found that electrons can become trapped within the oxide layer, and this electron trapping in the tunnel oxide reduces electric field during erase operations. In turn this gives rise to a in gradual degradation of the erase characteristics and closure of memory cell threshold window.

As a result charge trapping / de-trapping technology is key to the improvement of the flash memory wear characteristics.

Wear levelling

In order to gain the maximum use from a flash memory, a process called wear levelling is used. The wear levelling technique is one that can be used in a variety of forms of memory, e.g. hard drives, etc., but is also very applicable to flash memories where it is widely used.

The aim of the flash memory wear levelling functionality is to track which blocks have been used, and to distribute the programme and erase cycles are distributed evenly across the available memory. By using the wear levelling techniques, no block should be used greatly more than any other and therefore no single block prematurely fails due to a higher number of programme-erase cycles.

To achieve this, one block within the flash memory is designed to have an extended lifetime, so that it can be used to track the usage and control the wear levelling.

There are three main types of wear levelling mechanism that are used:

  • No wear levelling:   The simplest option is not to use wear levelling. This approach might be acceptable in circumstances where little use is expected and a reduction in complexity is of paramount importance. Under these circumstances the Flash memory controller permanently assigns the logical addresses from the operating system to the physical addresses of the Flash memory. When a location is changed, the contents of that block must be erased and then re-programmed without any intelligence to reduce the number of programme-erase cycles. This is not only more time consuming, but it also does nothing to reduce the flash memory wear.
  • Dynamic wear levelling:   Dynamic wear levelling uses a map to link Logical Block Addresses, LBAs generated by the operating system, OS, to the physical Flash memory locations. Each time the operating system writes new data, the map is updated so the original physical block is marked as invalid data. A new block is then linked to that map entry. Each time a block of data is re-written to the Flash memory it is written to a new location.

    There is still a problem with this type of flash memory wear levelling with blocks of data that never get replaced. They remain with no additional wear.

    The name for this type of wear levelling comes from the fact that only the dynamic data, i.e. data that is changed, is recycled. The memory may last longer than one with no wear levelling, but there will still be blocks of data that remain operable as a result of low usage, long after the memory as a whole is inoperable as some areas have exceeded the number of programme-erase cycles.
  • Static wear levelling:   This form of wear levelling is the most sophisticated and effective. Static wear levelling also uses a map to link the Logical Block Addresses to physical memory addresses.

    Static wear levelling works the same as dynamic wear levelling but with the addition that blocks of static data, i.e. data that does not change, are periodically moved so that these low usage cells are used by other data. By moving even static data periodically it levels the usage and hence levels the wear across the whole memory.

The various forms of wear levelling ensure that the maximum life is achieved for a flash memory. The wear levelling algorithms combined with improved semiconductor lifetimes, means that flash memory is an effective form of solid state memory.

By Ian Poole

<< Previous   |   Next >>

Share this page

Want more like this? Register for our newsletter

Clarifying Machine Vision with High Quality Sensors Mark Patrick | Mouser Electronics
Clarifying Machine Vision with High Quality Sensors
Automated imaging technology is everywhere we look. As cameras and their processing units get ever smaller, they are moving into ever more industries - from speed cameras and factory production lines to diagnostic medicine. For many of these applications, image quality is critical - but what does image quality really mean? Different applications will require quite distinct performance characteristics. Understanding camera specifications, differences between CCD and CMOS sensors, and features such as real-time processing or near-infrared (NIR) can help guide the camera selection process to produce better imaging results.

Radio-Electronics.com is operated and owned by Adrio Communications Ltd and edited by Ian Poole. All information is © Adrio Communications Ltd and may not be copied except for individual personal use. This includes copying material in whatever form into website pages. While every effort is made to ensure the accuracy of the information on Radio-Electronics.com, no liability is accepted for any consequences of using it. This site uses cookies. By using this site, these terms including the use of cookies are accepted. More explanation can be found in our Privacy Policy