17 Nov 2010

Integrated PLLs and VCOs for Wireless Applications

Ian Collins, Applications Engineer, RF Group, Analog Devices Inc. explains how to design PLLs and VCOs using integrated circuit chips.

Integrated Phase Locked Loops and Voltage Controlled Oscillator (VCO) integrated circuits (IC's) are now commonplace, and have been adopted for use in many wireless standards offering wider frequency range, flexibility and features compared to stand alone VCO's.

This article outlines some of the technical challenges posed by integrated PLL & VCO parts in wireless applications, and how to solve them.

The past decade has seen huge advances in the development of PLLs with integrated circuits. These advances have generally simplified design of Local Oscillator (LO) and clocking circuits, with a reduction in component count, wider frequency range and greater flexibility.

Some properties of integrated PLL & integrated VCO devices present new challenges to the RF engineer. With reference to the Analog Devices part, the ADF4350, we will take a more detailed look at these.

Multi-band VCO's

Stand-alone VCO's tend to have limited frequency ranges of 100 MHz or less. By contrast, the ADF4350 covers a frequency range from 137.5 - 4400 MHz by use of a multi-band VCO operating between 2.2 - 4.4 GHz, together with output dividers to realize lower frequencies.

Generally speaking, low VCO phase noise is dependent on high VCO tank circuit Q. A high VCO circuit Q implies small frequency range and sensitivity (Kv) of the VCO, a fundamental trade-off in VCO design. Many octave tuning VCO's solve this issue by extending the tuning voltage (VTUNE) to as high as 30 Volts, permitting a reduction in VCO sensitivity. But the ADF4350 solves this problem by dividing the frequency range into three separate VCO's, with sixteen VCO sub-bands in each VCO as shown below.

VCO frequency vs tune curve

VCO frequency vs tune curve

This necessitates a method of choosing the correct VCO band for each frequency update. Rather than use a look up table, which will not allow for manufacturing variations in band transitions, a VCO band select circuit is used which examines the output from the reference (R) and feedback (N) counters, and chooses the most appropriate VCO and sub-band for the programmed output frequency. This process necessitates a switching time, during which the open loop output frequency can be at a variety of different frequencies. This band select switching time is also added to the PLL lock time, which itself is a function of the PLL loop filter bandwidth. The ADF4350 contains a separate RF output stage after the VCO, which can be muted during the band select and PLL lock time, until the PLL lock detect asserts lock, and the output stage is automatically turned on. This mute till lock detect feature can be used to prevent any unwanted LO frequencies being generated during lock time and band select.

Power supplies

VCO pushing is measured by applying a steady dc tuning voltage to the ADF4350 VTUNE pin, varying the power supply voltage, and measuring the frequency change. The pushing figure (P) equals the frequency delta divided by the voltage delta, as shown in the table below.

ADF4350 VCO Pushing
VCO Frequency (MHz) VTUNE (V) VCO Pushing (MHz/V)
2200 2.5 0.73
3300 2.5 1.79
4400 2.5 5.99

In a PLL system, higher VCO pushing means that power supply noise will degrade the VCO phase noise. If VCO pushing is low, then power supply noise will not significantly degrade phase noise. However, for high VCO pushing, noisy power supplies will have a measurable impact on phase noise performance.

Experiments showed pushing to be at its maximum at 4.4 GHz VCO output frequency, so the comparison of VCO performance with different regulators was made at this frequency. Rev. A evaluation boards of the ADF4350 used the ADP3334 LDO regulator. The integrated rms noise of this regulator is 27 µV (integrated from 10 Hz to 100 kHz). This compares to 9 µV for the ADP150, which is used on the EVAL-ADF4350EB1Z, Rev B. In order to measure the impact of the power supply noise, a narrow PLL loop bandwidth (10 kHz) was used to facilitate greater examination of VCO phase noise.

A more detailed examination of the output noise density with frequency is available from the data sheets of both the ADP3334 and ADP150. The noise spectral density of the ADP3334 regulator is 150 nV/√Hz at 100 kHz offset. The same figure for the ADP150 shows 25 nV/√Hz.

The formula for calculating the degradation in phase noise due to the power supply noise is as follows:


Where L(LDO) is the noise contribution from the regulator to the VCO phase noise (in dBc/Hz), at an offset fm; P is the VCO pushing figure in Hz/V; Sfm is the noise spectral density at a given frequency offset in V/√Hz; and fm is the frequency offset at which the noise spectral density is measured in Hz.

  ADP3334 ADP150
Noise contribution from regulator (nV/√Hz) 150 25
Noise contribution from regulator (dBc/Hz) -104 -119.5
Total calculated noise at VCO output (dBc/Hz) -103 -109.5
Measured VCO noise at 100 kHz offset (dBc/Hz) -1-2.6 -108.5

ADF4350 Phase Noise at 4.4 GHz with ADP3334 Regulators

ADF4350 Phase Noise at 4.4 GHz with ADP3334 Regulators

ADF4350 Phase Noise at 4.4 GHz with ADP150 Regulators

ADF4350 Phase Noise at 4.4 GHz with ADP150 Regulators

The noise contribution from the supply is then rss summed with the noise contribution of the VCO (itself measured with a very low noise supply) to give the total noise at the VCO output with a given regulator. These noise performances are rss summed together to give the expected VCO phase noise:

VCO frequency vs tune curve

Or expressed in dB:

VCO frequency vs tune curve

In this example, a 100 kHz noise spectral density offset is chosen, a 6 MHz/V pushing figure is used, and ?110 dBc/Hz is taken as the VCO noise with an ideal supply.

Using a dedicated signal source analyzer (like Rohde & Schwarz FSUP), the VCO phase noise is compared. At 100 kHz offset the ADP3334 delivers 102.6 dBc/Hz, and in the same configuration the ADP150 measures 108.5 dBc/Hz. The integrated phase noise improves from 1.95° to 1.4° rms also. The measured results correlate very closely with the calculations and clearly show the benefit of using the ADP150 with the ADF4350. This underlines the importance of using low noise regulators for the VCO circuit of the ADF4350.

Loop Filter Design

On integer-N PLL's, the phase noise at offsets close to the carrier is dominated by the contribution from the PLL synthesizer. This is particularly the case with narrow-band systems like GSM which require 200 kHz spacing. The ADF4350 contains a fractional-N PLL which greatly reduces in-band noise compared to integer-N.

Using an integer-N PLL like the ADF4106, the in-band noise at 5 kHz offset (calculated from ADIsimPLL) is -95 dBc/Hz. Examining a suitable VCO for the application, the RFMD VCO 915-191U, the open-loop VCO phase noise at 5 kHz offset is -101 dBc/Hz, so in this case a smaller loop bandwidth than 5 kHz would permit lower rms phase error (or transit EVM). However, most integer-N PLL's for GSM applications are designed with 10-20 kHz loop filters, because a smaller loop filter will lead to a larger PLL lock time.

VCO-191-915U Open loop phase noise

VCO-191-915U Open loop phase noise

ADF4350 Open loop VCO phase noise

ADF4350 Open loop VCO phase noise

On the ADF4350, the open loop VCO phase noise tends to be comparable to the discrete VCO at offsets of 1 MHz or greater (-145 dBc/Hz), but at 5 kHz offset, the ADF4350 open loop VCO noise (for 915 MHz) is -81 dBc/Hz. However, because the ADF4350 contains a fractional-N PLL, the in-band noise contribution (from the PLL) at this same offset is -105 dBc/Hz. Since the PLL noise is lower than the VCO noise at the same offset it makes sense to increase the loop bandwidth to ~40 kHz, minimizing the rms phase error. This results in a 3x improvement in rms phase error compared to the Integer-N configuration (two graphs below). One can conclude from this experiment that it makes sense to use high PFD frequencies with loop filter bandwidths between 20 - 40 kHz on the ADF4350.

ADF4106 & external VCO, rms error 0.3°

ADF4106 & external VCO, rms error 0.3°

ADF4350, rms error 0.1°

ADF4350, rms error 0.1°

Another aspect of the ADF4350 loop filter design is the variation of the VCO sensitivity (Kv). The variation between the minimum Kv (18 MHz/V) to the maximum (58 MHz/V) can be a factor of 3x. Sensitivity varies in each VCO band (peaking in the middle of a band), and generally increases between bands as the frequency increases. Because of the large difference in Kv values, the geometric mean of VCO sensitivity is the most suitable value for PLL loop filter design. The graph of sensitivity below (Figure 8) shows two traces. The first (in bold) is the absolute sensitivity against frequency, and the second is the geometric mean of sensitivity for each VCO band, with a trend line added to give the geometric mean for each VCO band. The geometric mean of these sensitivities is approximately 33 MHz/V, which is close to the geometric mean of the two extremes of sensitivity listed above.

The implication is that for a given loop filter design, the geometric mean of the sensitivity for the maximum and minimum VCO frequency should be chosen. In practice, many applications will use the lowest and highest VCO frequencies (2.2 and 4.4 GHz), and in this case 33 MHz/V is recommended. In cases where a smaller subset of VCO frequencies is used then a more specific value of Kv is recommended. For example, if VCO frequencies 4.0 and 4.4 GHz are used, then, from the graph below, the geometric mean of 40 MHz/V (for 4.0 GHz) and 48 MHz/V (for 4.4 GHz) is 43 MHz/V. All of the above procedures are automatically followed in ADIsimPLL, and it is strongly recommended for low pass filter designs for the ADF4350.

ADF4350 with external PLL

Some applications may necessitate the use of an external PLL. These can include spur critical applications, or applications requiring sub-Hz resolution on the RF output. The ADF4350 contains a fractional-N PLL which is fabricated on the same die as the VCO. One effect of this is that spurs generated by the Reference (R) and Feedback (N) counters, the Phase Frequency Detector (PFD), and the sigma-delta could all easily couple to the VCO. Using an external PLL (ADF4153, ADF4156, ADF4157, ADF4150), and disabling the internal PLL can improve these spurs.

For applications requiring greater resolution at the RF output, a PLL such as the ADF4157 offers 25-bit modulus resolution, meaning that the Fractional part of the N divider, used with a 10 MHz PFD frequency, can generate frequency steps as small as 0.3 Hz. By contrast, the ADF4350 PLL contains a programmable 12 bit modulus (highest value 4095), which in a similar configuration to that above provides 2.5 kHz frequency resolution. Users wishing to achieve higher resolution can use the external PLL instead of the internal one.

VCO band select is still necessary and performed by the internal PLL, which can then be disabled after band select by holding the ADF4350 internal counters in reset (the counter reset feature). The spurious performance is improved by the greater isolation of the PLL circuitry from the VCO. The basic hardware connection is detailed below.

Use with Up/Down Converters

To achieve lower frequencies than 2200 MHz, it is necessary to use the output dividers on the ADF4350. Due to the architecture of the dividers, the output spectrum contains more harmonics, and at lower frequencies can resemble a square wave. If the part is to be used as the LO to a modulator or demodulator (mod's/demod's), it can be important to prototype the ADF4350 with the conversion stage to check the behaviour of the modulated/demodulated output.

On some mod/demods like the ADL5385, a divide by two stage exists after the LO input to the modulator, and the harmonic content of the LO is irrelevant as the necessary quadrature for up-conversion is generated by the divide by two circuit on the modulator. But, on some modulators like the ADL5375, the quadrature necessary for up-conversion is generated by a poly-phase filter, which can be sensitive to LO harmonic levels. High LO harmonics can degrade sideband suppression. In cases such as this, filtering of the harmonic levels is necessary to achieve the expected sideband performance. Figure For more information on this the circuit note CFTL-0134 contains more of the necessary detail.

Sideband Suppression for Filter b, 850 MHz to 2450 MHz

Sideband Suppression for Filter b, 850 MHz to 2450 MHz

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About the author

Ian Collins is an applications engineer for the RF Group at Analog Devices, Inc. He is responsible for both RF and microwave devices testing and development.

Analog Devices Inc is a leader in high performance signal processing solutions. The company ICs for data converters, amplifiers, DSP, RF & communications, power and thermal management, supervisory and interface, and MEMs. Develops analog, digital, linear, and mixed-signal integrated circuits including data converters, amplifiers, DSP, RF, and more.

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