07 Jan 2013
Hitachi Cable deploys ALINTT from Aldec
Aldec, reveals that Hitachi Cable has adopted ALINT as a part of the RTL review and validation process in their corporate FPGA design flow.
"Verification takes up to 70% of entire design cycle, so we believe in starting verification tasks at the very early stages of design flow when cost and efficiency of fixing bugs are optimal", said Koichiro Seto, General Manager, Hitachi Cable Core Technology Dept. "Since we started using ALINT, we have identified several critical problems in our current RTL design, including complex hierarchical issues that would otherwise result in excessive routing delays."
According to Aldec, Hitachi Cable performed an extensive analysis of ALINT on one of their current designs targeting the largest FPGA available market today.
The product achieved the required critical mass from the engineering divisions to be deployed in its FPGA design flow to ensure early bug detection, perform automated code reviews and enforce uniform RTL coding style across the organization.
Dmitry Melnik, Product Manager, Aldec Software Division, said: "With FPGA designs being no simpler than ASICs nowadays, we are seeing more and more interest for traditionally ASIC tools and design policies from FPGA design teams. Well-known for a large FPGA user base, Aldec has incorporated many features key to the FPGA designers into ALINT, including the unique support for FPGA vendor primitives, precompiled FPGA vendor libraries, and lowest false violation ratios."
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