17 Sep 2012

Aldec enters the ASIC prototyping market with HES-7

Aldec Europe has unveiled the HES-7, an FPGA-based ASIC/SoC prototyping system that promises hardware verification and software verification teams a versatile solution and lowers the cost of the prototyping process.

HES-7 takes advantage of the Xilinx Virtex-7 2000T 3D IC, which affords a design capacity of up to 24 million ASIC gates on a single, dual-device HES-7 board.

In addition, the system employs a non-proprietary high-speed backplane connector that enables easy expansion of custom daughter boards or which can facilitate the connection of up to four HES-7 boards, delivering a total design capacity of up to 96 million ASIC gates.

Zibi Zalewski, Hardware Division General Manager at Aldec, comments: “Prototyping is beneficial to the whole ASIC delivery process, and the most common way to prototype is to use FPGAs. However, with most ASIC designs being between 10 and 20 million gates, to date it has been necessary to employ several low-density FPGAs on a single prototyping board; and implementing the SoC/ASIC design has been a painful and costly process because the design needs to be partitioned between the multiple devices."

"Using a dual-chip HES-7 prototyping solution from Aldec, equipped with Xilinx’s industry-leading Virtex-7 2000T devices, reduces the design implementation effort and lowers the tool expense when supporting multi-million gate SoC designs,” he says.

Kirk Saban, Sr. Product Line Manager, Virtex-7 Xilinx, added: “The HES-7 product fully leverages the power of our Virtex-7 2000T devices and our Vivado Design Suite, which together... accelerate time-to-validation and drive down the cost of the ASIC prototype process.”

HES-7 is available in four different board configurations, which afford capacities of between 4 and 96 million ASIC gates.

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