23 May 2013
TSMC certifies Cadence Tempus Timing Signoff at 20nm
TSMC has certified the new Tempus Timing Signoff Solution from Cadence Design Systems, at 20nm.
The certification means the Cadence Tempus Timing Signoff Solution passes TSMC’s rigorous EDA tool certification to enable customers to achieve accuracy required for advanced technologies.
“Tempus timing signoff technology elevates timing analysis performance to a new standard by leveraging distributed processing and innovative incremental timing technology,” said Anirudh Devgan, corporate vice president, Silicon Signoff and Verification, Silicon Realization Group at Cadence. “We worked closely with TSMC to ensure that Tempus results met their strict criteria that leads to working silicon and robust designs.”
TSMC accuracy certification requirements for the Tempus Timing Signoff Solution spanned base delay calculation and signal integrity with glitch bump calculation. These two areas are required in order to have a complete timing and signal integrity analysis solution.
“Certification is an integral part of TSMC’s overall design ecosystem,” said Suk Lee, TSMC senior director, design infrastructure marketing division. “Cadence Tempus timing signoff tools are ready to address the design challenges of future TSMC process nodes. We worked closely with Cadence so Tempus could pass our acceptance criteria, and we look forward to teaming with them on future technologies.”
Most popular news in Design principlesInvenSense appoints Avnet for MotionTracking in Europe
Cadence certified for TSMC 16nm FinFETs
LabVIEW compatible with LEGO MINDSTORMS robots
Extraction tool for faster FinFETs
Next-gen development suite reduces project verification time
Share this page
Want more like this? Register for our newsletter