24 May 2018

Full-flow digital and signoff tools certified on Samsung’s 8LPP tech

Cadence Design Systems has announced that its full-flow digital and signoff tools have achieved certification for Samsung Foundry’s 8-nanometer (nm) Low Power Plus (LPP) process.

The tools were certified for the Process Design Kit (PDK) and foundation library on the 8LPP process and confirmed to meet Samsung Foundry’s accuracy requirements, enabling system and semiconductor companies to accelerate the delivery of 8LPP designs. The Cadence RTL-to-GDSII design flow that has been certified for the 8LPP process technology is based on the Design Methodology (DM) of Samsung Foundry using an OpenRISC OR1200 design.

The Cadence digital and signoff tools are available via a quick-start kit. The certified tools include the Innovus Implementation System, Genus Synthesis Solution, Joules RTL Power Solution, Conformal Equivalence Checking, Conformal Low Power, Modus DFT Software Solution, Voltus IC Power Integrity Solution, Tempus Timing Signoff Solution, Quantus Extraction Solution, Physical Verification System (PVS), Cadence CMP Predictor (CCP) and Cadence Litho Physical Analyzer (LPA).

“Our 8LPP process delivers optimized power, performance and area over previous generations of advanced FinFET nodes and is expected to provide great benefits for applications including mobile, networking, server and automotive designs,” said Ryan Lee, vice president of Foundry Marketing at Samsung Electronics. “We’ve been working closely with Cadence to ensure that customers can quickly and easily experience the benefits of this advanced process technology using the certified Cadence digital and signoff full-flow.”

“Our mutual customers can create high-performance designs using the 8LPP process and get to market faster due to Samsung Foundry’s certification of our RTL-to-GDSII reference flow,” said KT Moore, vice president, product management in the Digital & Signoff Group at Cadence. “Our ongoing collaboration with Samsung Foundry demonstrates our commitment to enabling advanced-node innovation.”

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