14 Jan 2014
Cadence Compiler speeds Renesas IP development
Cadence Design Systems reveals that Renesas Electronics shortened its design and verification time by 70 percent by utilizing Cadence C-to-Silicon Compiler to develop High Efficiency Video Coding (HEVC) intellectual property (IP), targeting consumer 4K video devices.
This enabled the company to quickly offer their customers IP supporting this next-generation video codec.
Renesas established its own coding style and reduced code size by almost half with SystemC to create the HEVC IP at a high level of abstraction.
This enabled verification times that were six times faster than register-transfer level (RTL). This approach also enabled Renesas to use C-to-Silicon Compiler to explore many algorithmic implementations to generate high-performance RTL while minimizing power consumption and chip area.
To eliminate any potential schedule impact from a significant engineering change order (ECO) late in the project, Renesas developed an ECO flow utilizing C-to-Silicon Compiler with Encounter® Conformal® ECO Designer. This allowed them to use high-level synthesis to quickly apply and verify a patch to stay on schedule.
“The challenge with developing this HEVC/H.265-compliant IP was to incorporate our proprietary new algorithm, which enables high quality and high compression efficiently,” said Toyokazu Hori, department manager of Platform Base Technology Development Department, Automotive Information System Business Division at Renesas Electronics Corporation. “Deploying the system-level design approach with C-to-Silicon Compiler for the entire design addressed this challenge and we were able to implement the new algorithm very efficiently, achieving a good time-to-market for our advanced new IP.”
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