21 May 2015
Updates to Allegro portfolio make design cycles shorter
Cadence Design Systems has unveiled the Allegro 16.6 portfolio, which features several new products and technologies. Included in this release is the new Allegro PCB Designer Manufacturing Option, which can shorten the time to create manufacturing documentation by up to 60 percent, and several key technology updates catered to increase efficiency, control and productivity for designers, while streamlining handoff to manufacturing.
Driven by increasing demands to provide a more predictable and shorter design cycle, the Allegro 16.6 portfolio includes more capabilities that accelerate routing and tuning for high-speed interfaces such as DDR3 and DDR4. It aims to help PCB designers achieve maximum efficiency and productivity, while keeping cost of ownership low.
These new products include:
Allegro PCB Designer Manufacturing Option a powerful, easy-to-use toolset that makes it efficient and cost effective for PCB designers to streamline the development of a release-to-manufacturing package for their products. It includes the Design for Manufacturing (DFM) Checker, Documentation Editor and Panel Editor modules. The Documentation Editor module can speed up overall fabrication documentation by up to 60 percent.
**Allegro Rules Developer and Checker ** which allows users to develop custom fabrication and assembly rules to extend capabilities provided by Allegro PCB Designer and the Manufacturing Option. This tool provides a relational geometric verification language designed specifically for creating rules that are proprietary and custom to an original equipment manufacturer (OEM). The rules can be viewed and executed from the Allegro Constraint Manager, making it a single source for all design rules checks (DRCs) within a PCB.
"We use Cadence software for designing printed circuit boards from concept to production for our SGI ICE X and SGI UV platforms. The technology in the Allegro PCB Manufacturing Option has enabled us to reduce the amount of time spent creating and maintaining PCB documentation by as much as 60 percent", said Cassio Conceicao, executive vice president and chief operating officer. "The result is shorter design cycle times, lower costs and a smoother handoff to manufacturing.
Adding return path vias while routing differential pairs, ensuring a ground current return path for differential pair vias
Updates to avoid coupling of high-speed signals to the FR-4 fabric weave, making it easy for designers to create off-angle routes based on user-defined parameters, accelerating the PCB layout process significantly
Adjusting spacing for signals in interfaces such as DDR3 and DDR4, allowing users to compress signals in high-density route areas, and to spread signals to avoid crosstalk between signals or make space for tuning
A new shape-editing AppMode, allowing users to create and modify complex shape geometries very easily and quickly for copper shapes, flex cover lay geometries and complex pad shapes
"The Allegro portfolio release targets critical design goals for PCB designers who are focused on increasing productivity, while operating under tight schedules and increasing complexities", said Saugat Sen, vice president of R&D, PCB and IC Packaging Group at Cadence. "To make the design process more efficient, Cadence introduced the Allegro Rules Developer and Checker, which provides a relational geometric verification language that enables designers to extend the standard set of rules to ones that are tailored to their needs."
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