21 Jan 2016
Cadence Sigrity 2016 portfolio improves product creation time
Cadence Design Systems has announced the availability of the Sigrity 2016 technology portfolio, which improves product creation time with an enhanced PCB design and analysis methodology that is ideal for multi-gigabit interfaces.
To speed up the qualification of a physical design for the USB Implementers Forum (USB-IF) compliance test, the Cadence Sigrity technology portfolio includes automated support for IBIS-AMI model creation, fast and accurate channel model extraction using multiple field solvers, and an automated power-aware signal integrity analysis report to validate a virtual USB 3.1 channel. These technologies, when used together, can shave weeks off the design process.
Previously, IBIS-AMI model creation has been a manual process. The Sigrity 2016 technology portfolio now leverages validated equalization algorithms used by the Cadence Design IP SerDes PHY team and provides an automated methodology for combining, paramaterizing and compiling the algorithms into an executable model. This can increase the pool of engineers capable of efficiently developing SerDes I/O models.
The new cut and stitch technology features the ability to create accurate channel models ten times faster by using a mix of hybrid and 3D full-wave field solvers. With minimal manual intervention, the serial link channel can be divided into sections, solved for and automatically stitched together into a single interconnect model. The rapid model extraction technique enables engineers to trade-off various signal routing and layer transition strategies and still meet demanding time-to-market requirements.
Other capabilities that have been enhanced in the portfolio are:
New quasi-static 3D field solver integrated with 3D full wave and hybrid solver technology available for both IC package and PCB analysis
Electrical Performance Assessment integrated directly into the IC Package Designers layout environment
Optimized decoupling capacitor schemes updated to Allegro PCB layout
Improved Power Integrity analysis methodology for PCB designers
"The Sigrity 2016 portfolio features capabilities that increase efficiency and speed up the design process by enabling designers to qualify multi-gigabit standard interfaces such as USB 3.1", said Vinod Kariat, vice president of Custom IC and PCB Group R&D at Cadence. "These features remove the need to manually write and compile code using a software development environment to create SerDes I/O models and that makes modeling of transceivers and interconnects faster".
"Our collaboration with Cadence has allowed both engineering teams to develop tools that can improve our joint customers' product creation process. The Sigrity 2016 release aligns with our customers needs to address serial link analysis challenges as early as possible", said Brian Reich, General Manager Performance Oscilloscopes, Tektronix. "Together we can help our joint customers reduce weeks from their design cycles as they prototype USB 3.1 interfaces with the Sigrity solution and validate them in the lab with the Tektronix solutions".
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