Boundary Scan, JTAG Interface

- an summary of the JTAG, Boundary Scan interface and JTAG, boundary scan bus description and the use of a JTAG connector.

In order to be able to use JTAG, boundary scan test techniques it is necessary to have the correct JTAG interface. Often a special JTAG connector may be added to enable the connections to be made easily for test. In this way it is possible for the test signals to be handled by the board or item under test. The JTAG interface consists primarily of a serial bus with four signals.

The four required signals for a JTAG interface are:

• TCK



• TMS



• TDI



• TDO

JTAG interface signals

The four signals that form the JTAG interface are given below with associated descriptions. Often these connections may be contained within a special JTAG connector fitted to the item under test to enable easy access for test.

TCK     Test Clock - this pin within the JTAG interface is the clock signal used for ensuring the timing of the boundary scan system. The Test Clock is used to load the test mode data from the TMS pin, and the test data on the TDI pin on the rising edge. On the falling edge test clock outputs the test data on the TDO pin. It is important that the clock line is properly terminated to prevent reflections that may give rise to false triggering and incorrect operation of the JTAG interface.

TDI     Test Data Input - Test instructions shift into the device through this pin. It receives serial input data which is either feed to the test data registers or instruction register, dependent upon on the state of the TAP controller. The TDI line has an internal pull-up, and therfore the input is high with no input.

TDO     Test Data Output - This pin within the JTAG interface provides data from the boundary scan registers, i.e. test data shifts out on this pin. It delivers serial data which comes from either the test data registers or instruction register, dependent upon on the state of the TAP controller. Data applied to the TDI pin will appear at the TDO pin but may be shifted by a number of clock cycles, depending on the length of the internal register. The TDO pin has a high-impedance.

TMS     Test Mode Select - This input on the JTAG interface also clocks through on the rising edge of TCK determines the state of the TAP controller. It controls the operation of the test logic, by receiving the incoming data. The value at the input on the rising edge of the clock controls the movement through the states of the TAP controller. The TMS line has an internal pull-up, and therefore the input is high with no input.

ICs supporting boundary scan will have the four pins listed above as the JTAG interface, and these may possibly included on a separate JTAG connector. Devices residing on the bus are connected in a daisy chain format, i.e. one to the next and so forth in a serial fashion. The TDO pin of one device connects to the TDI pin of the next device.

TRST     Test Reset - This is an optional active low test reset pin on the JTAG interface. It permits asynchronous TAP controller initialization without affecting other device or system logic.

In addition to having the pins listed above each device most have a Boundary-Scan Register. The Boundary-Scan Register may be used to test the interconnection between ICs [Chip-to-Chip] or test with in the IC