|
|
|||
![]() |
|||
|
|
|||
|
Navigation:: Home >> Electronics tutorials >> Radio receiver technology >> this page Phase locked loop, PLL, tutorial- an introduction to the phase locked loop, PLL, and how it operates
The phase locked loop or PLL is a particularly flexible circuit building block. The phase locked loop, PLL can be used for a variety of radio frequency applications, and accordingly the PLL is found in many radio receivers as well as other pieces of equipment. The phase locked loop, PLL, was not used in early radio equipment because of the number of different stages required. However with the advent of radio frequency integrated circuits, the idea of phase locked loops, PLLs, became viable. Initially relatively low frequency PLLs became available, but as RF IC technology improved, so the frequency at which PLLs would operate rose, and high frequency versions became available. Phase locked loops are used ain a large variety of applications within radio frequency technology. PLLs can be used as FM demodulators and they also form the basis of indirect frequency synthesizers. In addition to this they can be used for a number of applications including the regeneration of chopped signals such as the colour burst signal on an analogue colour television signal, for types of variable frequency filter and a host of other specialist applications Concepts - phase To understand more about the concept of phase and phase difference, first visualise a radio frequency signal in the form of a familiar x-y plot of a sine wave. As time progresses the amplitude oscillates above and below the line, repeating itself after each cycle. The linear plot can also be represented in the form of a circle. The beginning of the cycle can be represented as a particular point on the circle and as a time progresses the point on the waveform moves around the circle. Thus a complete cycle is equivalent to 360 degrees. The instantaneous position on the circle represents the phase at that given moment relative to the beginning of the cycle. To look at the concept of phase difference, take the example of two signals. Although the two signals have the same frequency, the peaks and troughs do not occur in the same place. There is said to be a phase difference between the two signals. This phase difference is measured as the angle between them. It can be seen that it is the angle between the same point on the two waveforms. In this case a zero crossing point has been taken, but any point will suffice provided that it is the same on both. When there two signals have different frequencies it is found that the phase difference between the two signals is always varying. The reason for this is that the time for each cycle is different and accordingly they are moving around the circle at different rates. It can be inferred from this that the definition of two signals having exactly the same frequency is that the phase difference between them is constant. There may be a phase difference between the two signals. This only means that they do not reach the same point on the waveform at the same time. If the phase difference is fixed it means that one is lagging behind or leading the other signal by the same amount, i.e. they are on the same frequency. PLL basics A basic phase locked loop, PLL, consists of three basic elements:
PLL operation The Voltage Controlled Oscillator, VCO, within the PLL produces a signal which enters the phase detector. Here the phase of the signals from the VCO and the incoming reference signal are compared and a resulting difference or error voltage is produced. This corresponds to the phase difference between the two signals.
Block diagram of a basic phase locked loop (PLL) The error signal from the phase detector in the PLL passes through a low pass filter which governs many of the properties of the loop and removes any high frequency elements on the signal. Once through the filter the error signal is applied to the control terminal of the VCO as its tuning voltage. The sense of any change in this voltage is such that it tries to reduce the phase difference and hence the frequency between the two signals. Initially the loop will be out of lock, and the error voltage will pull the frequency of the VCO towards that of the reference, until it cannot reduce the error any further and the loop is locked. When the PLL is in lock a steady state error voltage is produced. By using an amplifier between the phase detector and the VCO, the actual error between the signals can be reduced to very small levels. However some voltage must always be present at the control terminal of the VCO as this is what puts onto the correct frequency. The fact that a steady error voltage is present means that the phase difference between the reference signal and the VCO is not changing. As the phase between these two signals is not changing means that the two signals are on exactly the same frequency. Summary
|
|
||||||||||||||||||
| This
site is operated and owned by Adrio Communications Ltd and edited by Ian Poole. All information
is © Adrio Communications Ltd and may not be copied except for individual personal use. This includes copying material in whatever form into website pages While every effort is made to ensure the accuracy of the information on this site, no liability is accepted for any consequences of using it. By using this site, these terms are accepted. Privacy Policy |
||||