SDRAM Operation & Timing

- overview of the operation of SDRAM with details of timing and control signals.

SDRAM tutorial includes:

    •  SDRAM basics
    •  SDRAM architecture
    •  SDRAM operation & timing
    •  DDR SDRAM
    •  DDR2 SDRAM
    •  DDR3 SDRAM
    •  DDR4 SDRAM
    •  JEDEC 79 DDR standard

There are many elements to SDRAM operation - the SDRAM timing is one key issue as it enables much faster speeds to be achieved than with traditional DRAM.

SDRAM operation also has a number of lines that control the operation and timing issues. These lines are familiar to many designers of processor circuits, although there are naturally issues of operation and timing that are different to other forms of memory.

SDRAM control signal operation

The asynchronous operation of DRAM caused many design challenges because it interfaced to a synchronous processor system. These issues became more apparent as the processor speeds increased.

As the term synchronous used within the title SDRAM (synchronous dynamic random access memory) indicates, this form of memory runs in a synchronous fashion. To achieve this the commands are timed relative to the rising edge of the clock.

There are various actions that can be taken by the memory. These are determined by the state of the command signals at the rising edge of the clock.

There are six control signals that are used for SDRAM operation.

• /CAS Column Address Strobe   Along with /RAS and /WE, this control line on the SDRAM selects one of 8 commands.
• CKE Clock Enable   When this signal is low, and after one clock cycle, the SDRAM is inhibited and no commands are interpreted despite the state of other lines.
  
  The SDRAM is made active on the rising edge of the clock after CKE is made high.
• /CS Chip Select   This line is used when several chips are used together and it enables selection of a particular SDRAM. When this line is high, the chip ignores all other inputs except for CKE.
• DQM Data Mask   The DQM line is used to suppress the I/O data when it is high. For read actions, when the DQM line is asserted high two cycles before a read cycle, the read data is not output from the chip.
  
  There is one DQM line per 8 bits on a x16 memory chip or DIMM
• /RAS Row Address Strobe   The /RAS line is a command bit which enables election of one of eight commands when it is asserted along with /CAS and /WE.
• /WE Write enable   This line is generally used in conjunction with /CAS and /RAS, but it normally distinguishes read-like from write-like commands.

There are many commands that can be sent. Most operations comprise a number of different commands. For example a typical sequence may comprise the following commands:

1. Activate:   This sends a row address to the SDRAM to open a row, i.e. page.
2. Deselect commands:   These commands within the overall SDRAM operation satisfy the timing requirements for the memory.
3. Read or Write:   This is sent with the column address. With a row open, several read or write commands can be undertaken. This enables much faster activity as new rows do not need to be opened or deactivated.
4. Precharge :   A precharge command is required to close a row before a new row can be opened.

SDRAM timing

SDRAM has significant advantages over the more traditional RAM. One of the ways it has been able to achieve this is by utilising the timing of the system to achieve more efficient usage of time. Hence SDRAM timing is of great importance.

There are a number of SDRAM timings that are of great importance:

• Read cycle time:   This element of SDRAM timing is the time between successive read operations to an open row. Typical figures are of the order of 5 ns.
• CAS latency:   The CAS latency is the time between supplying a column address and then receiving back the corresponding data. For any system, the CAS latency is programmed into the SDRAM's mode register and expected by the DRAM controller. It is defined in terms of a specific number of clock cycles.

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