Dynamic RAM, DRAM Operation & Function

- operation and function of the dynamic RAM, DRAM, detailing how DRAM chips work and how they are used within a circuit.

DRAM is a form of semiconductor memory, but it operates in a slightly different way to other formats.

In order to be able to design and use DRAM, it is obviously wise to be able to have an understanding about the DRAM operation and its functionality.


DRAM operation basics

DRAM memory technology has MOS technology at the heart of the design, fabrication and operation. The basic dynamic RAM or DRAM memory cell uses a capacitor to store each bit of data and a transfer device - a MOSFET - that acts as a switch.

The level of charge on the memory cell capacitor determines whether that particular bit is a logical "1" or "0" - the presence of charge in the capacitor indicates a logic "1" and the absence of charge indicates a logical "0".

The basic dynamic RAM memory cell has the format that is shown below. It is very simple and as a result it can be densely packed on a silicon chip and this makes it very cheap.

Circuit diagram of a typical memory cell from a DRAM chip
Dynamic RAM memory cell

Two lines are connected to each dynamic RAM cell - the Word Line (W/L) and the Bit Line (B/L) connect as shown so that the required cell within a matrix can have data read or written to it.

The basic memory cell shown would be one of many thousands or millions of such cells in a complete memory chip. Memories may have capacities of 256 Mbit and more. To improve the write or read capabilities and speed, the overall dynamic RAM memory may be split into sub-arrays. The presence of multiple sub-arrays shortens the word and bit lines and this reduces the time to access the individual cells. For example a 256 Mbit dynamic RAM, DRAM may be split into 16 smaller 16Mbit arrays.

The word lines control the gates of the transfer lines, while the bit bines are connected to the FET channel and are ultimately connected to the sense amplifiers.

There are two ways in which the bit lines can be organised:

  • Folded Bit Lines:   It is possible to consider a pair of adjacent bit lines as a single bit line folded in half with the connection on the fold broken and connected to a shared sense amplifier. This format provides additional noise immunity, but at the expense of being less compact.
  • Open Bit Lines:   In this configuration the sense lines are placed between two sub-arrays, thereby connecting each sense amplifier to one bit line in each array. This offers a more compact solution than the folded bit lines, but at the expense of noise immunity.


Dynamic RAM read / write

One of the critical issues within the dynamic RAM is to ensure that the read and write functions are carried out effectively. As voltages on the charge capacitors are small, noise immunity is a key issue.

There are several lines that are used in the read and write operations:

  • /RAS, the Row Address Strobe:   As the name implies, the /RAS line strobes the row to be addressed. The address inputs are captured on the falling edge of the /RAS line. The row is held open as long as /RAS remains low.
  • /CAS, the Column Address Strobe:   This line selects the column to be addressed. The address inputs are captured on the falling edge of /CAS. It enables a column to be selected from the open row for read or write operations.
  • /WE, Write Enable:   This signal determines whether a given falling edge of /CAS is a read or write. Low enables the write action, while high enables a read action. If low (write), the data inputs are also captured on the falling edge of /CAS.
  • /OE, Output Enable:   The /OE signal is typically used when controlling multiple memory chips in parallel. It controls the output to the data I/O pins. The data pins are driven by the DRAM chip if /RAS and /CAS are low, /WE is high, and /OE is low. In many applications, /OE can be permanently connected low, i.e. output always enabled if not required for example of chips are not wired in parallel.

Dynamic RAM refresh

One of the problems with this arrangement is that the capacitors do not hold their charge indefinitely as there is some leakage across the capacitor. It would not be acceptable for the memory to lose its data, and to overcome this problem the data is refreshed periodically. The data is sensed and written and this then ensures that any leakage is overcome, and the data is re-instated.

One of the key elements of DRAM memory is the fact that the data is refreshed periodically to overcome the fact that charge on the storage capacitor leaks away and the data would disappear after a short while. Typically manufacturers specify that each row should be refreshed every 64 ms. This time interval falls in line with the JEDEC standards for dynamic RAM refresh periods.

There are a number of ways in which the refresh activity can be accomplished. Some processor systems refresh every row together once every 64 ms. Other systems refresh one row at a time, but this has the disadvantage that for large memories the refresh rate becomes very fast. Some other systems (especially real time systems where speed is of the essence) adopt an approach whereby a portion of the semiconductor memory at a time based on an external timer that governs the operation of the rest of the system. In this way it does not interfere with the operation of the system.

Whatever method is use, there is a necessity for a counter to be able to track the next row in the DRAM memory is to be refreshed. Some DRAM chips include a counter, otherwise it is necessary to include an additional counter for this purpose.

It may appear that the refresh circuitry required for DRAM memory would over complicate the overall memory circuit making it more expensive. However it is found that DRAM the additional circuitry is not a major concern if it can be integrated into the memory chip itself. It is also found that DRAM memory is much cheaper and has a much greater capacity than the other major contender which might be Static RAM (SRAM).


DRAM size considerations

One important element within the design of DRAM memory chips is the signal to noise ratio. This depends upon the ratio of the capacitance of the storage capacitor within the DRAM memory to the capacitance of the Word or Bit line on which the charge is dumped when the cell is accessed. As the bit density per chip is increased, the ratio is degraded since the cell area is decreased as more cells are added on the bit line. It is for this reason that it is important to store as high a voltage on the cell capacitor, and also to increase the capacitance of the DRAM storage capacitor for a given areas as much as possible.

This is a very important consideration because sensing the small charge on the memory cell capacitor is one of the most challenging areas of the DRAM memory chip design. As a result of this some elaborate circuit designs have been incorporated onto DRAM memory chips.

By Ian Poole


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