Navigation:: Home >> Electronic components >> this page

ASIC Design Development and Layout

- an overview or tutorial of the basics of the design, development and layout processes for ASIC, Application Specific Integrated Circuits.

ASIC, Application Specific Integrated Circuit can be very costly to produce. As a result, it is necessary to ensure that the ASIC design and development process is undertaken in a logical and controlled manner.

Each stage of the ASIC design and development process should be carefully monitored and precautions taken to ensure that the final ASIC design meets the requirement and operates satisfactorily in real world applications.

ASIC design and development stages

There are several stages in an Application Specific Integrated Circuit, ASIC design. Each must be undertaken correctly because errors later in the process become progressively more costly to correct. Ideally the development process should incorporate all the required stages, and each one should be completed satisfactorily before moving on to the next. Often an external specialist company is used to provide the ASIC design service. Accordingly it is necessary to ensure that the interface to the ASIC design service or company is fully functional. One way of doing this is to ensure that the ASIC design process is correct.

Requirements capture     In just the same way that capturing the requirements is an essential part of any systems design, the same is true of an ASIC design. It is essential that all the requirements are captured so that the design can be set in place correctly. Changes to the requirements at a later stage will result in design changes that will cost a significant amount to implement.

Modelling     At this stage of the ASIC development it is necessary to model the high level functionality of the ASIC design to ensure that the correct approach has been taken. This modelling is normally done in software, often in C or a similar language. In some circumstances it is possible to import the circuit block diagram into the design tool to enable the ASIC modelling to be undertaken.

One very important area of the ASIC modelling at this stage is to ensure that the truncation and rounding elements are incorporated correctly. Any mismatch can create large problems later in the design that can be difficult to locate and correct.

ASIC package selection     The choice of package for the ASIC is governed by a number of factors. Obviously the number of connections required has a major influence, but so does the anticipated heat dissipation. Higher levels of heat dissipation will require a package that can transfer the heat from the silicon very effectively. In addition to this the anticipated manufacturing process for the circuit into which the ASIC is to be incorporated will also have an impact. Finally the vendor of the ASIC silicon will affect the choice of package. Different ASIC vendors will offer different packages. Accordingly the final choice will be a balance between all the requirements.

The available packages for ASICs can be chosen from a number of the familiar packages used for large scale integrated circuits and include:

  • Quad flat pack (QFP) - although once popular and providing a high level of connectivity, these packages are not robust and are easily damaged. The pins are easily bent prior to soldering onto the target board and as a result very careful handling is required.
  • Ball grid array (BGA) - this is often the preferred solution now as BGAs are robust and can be handled in most SMT manufacturing processes.

ASIC design capture     The design capture for the ASIC can be achieved in a number of ways. Once of the most obvious methods is to capture the ASIC design from a schematic. This method has been superseded and the designs are normally designed using design tools that capture the mathematical operations required and convert this into the required circuitry representation. There are a number of tools that can perform this including VHDL design tools and Verilog. These tools can control the design at both the high or low level of the design. This enables control of the ASIC design down to the register by register or even the bit by bit level.

ASIC layout

The ASIC layout is an important stage in the development. The level of customisation of the ASIC layout will depend upon the type of ASIC being used, but for full customised designs, the ASIC layout is far more flexible than for the other versions where it may not be possible to determine large elements of the layout.

The ASIC layout will involve many factors from the most convenient proximity of certain sections of the circuit and transit times, to the number of interconnections that need to be made between different areas. The ASIC layout is normally undertaken under computer control, but is nevertheless possible to place restrictions on the ASIC layout to ensure that certain electrical parameters are met.

ASIC simulation and comparison with modelling     Once the design of the ASIC has been captured, it is necessary to ensure that the design will meet its requirements and that it will work correctly. Further simulation is undertaken to achieve this. The ASIC design is checked against the software model generated previously. It is found that many of the errors discovered in the final integrated circuit are functional errors that could often be found at this stages if the modelling is a realistic representation of the target or required ASIC functionality. Additionally a careful check of the timing is essential, especially for full custom ASIC designs. This needs to be performed over slightly more than the specified temperature range, the power supply input range and the envisaged process variation.

Formal verification     This area of the ASIC design lifecycle has become increasing important in recent years. With the growing complexity of ASIC designs, it has become more important to undertake a formal verification to ensure that the design is correct. Aspects including checks to ensure that all the variables within the software model are correctly defined, as well as checking for aspects such as clock skew, and metastability between different clocked areas of the ASIC design. The metastability is a problem that occurs when data changes at the same instant as the clock. It is the probability versus time to settle of the output data not settling to the required state if the input data and clock change at the same time.

ASIC test techniques     Once manufactured, it is necessary to be able to test the ASIC device. Three techniques are normally considered for use. The first is boundary scan, JTAG, IEEE1149.1. Using this technique it is possible to check the input/output areas, and also the internal circuitry within the device. However boundary scan is a serial technique and it is too slow to check much of a complex device.

The second technique uses what are termed scan chains. This technique uses the existing registers from the ASIC, but each one incorporates a multiplexer between the scan input and the normal input. A number of chains can be set up, each having two inputs and an output chain. Test vectors are generated for the inputs and using these it is then possible to analyse the output and detect any errors. Automated scan chain input sequences can be generated and optimised to test all the logic between the registers to check for nodes that may be stuck in a particular state, i.e. 1 or 0.

To speed the ASIC test process a number of chains can be implemented, thereby enabling parallel testing to be accomplished.

Additionally BIST (Built In Self Test) may be used. This is particularly useful in situations such as the test of chips incorporating elements such as SRAM which take a long time to check. Often vendors sell what are termed "canned vectors" for the test of such elements. As these are very cost effective in terms of silicon area and test time. The technique and extent of these vectors can often influence the choice of vendor.

Physical test of prototype ASICs     When the physical prototype silicon ASICs are available it is necessary to give them a complete test, including a test with the ASIC in the target circuit. Not only is it necessary to check their operation, but in addition to this, checks of the process spread are undertaken to give an indication of the likely yield in production. The aim is a narrow spread that is not close to pass fail limit edges.

It is possible that some problems will be found at this stage. To investigate the problems a number of techniques can be used. Boundary scan is one powerful tool, and checks can also be made around the interface to the external circuitry. One technique that was used successfully was to probe directly onto the ASIC silicon itself. This is not normally possible now in view of the very small feature sizes that are commonplace today.

Another techniques is to investigate the symptoms and then generate a hypothesis that can then be tested against the simulation of the ASIC. This enables the correct problem to be simulated and then corrected.

Lifecycle reviews & handover to manufacture     As with any interface between departments or different areas of a development team it is necessary to ensure that the interfaces operate satisfactorily, and that all the required information is passed over accurately. This is particularly true of the interface with the silicon vendor as they form a different company and will have different processes by which they work. To achieve this, the handover of information to and from the ASIC design service is normally done on a formal basis, and the silicon vendors will often expect to see many items including the verification results for the ASIC design, as part of this.


If the ASIC design process is undertaken carefully, it is possible to reap very large benefits in terms of reduce unit cost and often improvements in performance. However if errors enter the process, the development costs can increase as further iterations of the ASIC design and development process are required. Accordingly care is needed to ensure the ASIC development is accomplished successfully.

By Ian Poole

Further pages from this tutorial
Page [ 1 ] >> [ 2 ] >>

Want more like this? Register for our newsletter

Securing wireless data transport Bernd Hantsche | Rutronik
Securing wireless data transport
Wireless communication is part of the critical infrastructure of our lives, enabling services as diverse as TV and radio, smartphones, remote monitoring, garage-door openers and a rapidly expanding family of Internet of Things devices.
Online - Fundamentals of Modern RF and Wireless Communications Engineering
This on-line course enables you to quickly get up-to-speed & understand key concepts of modern radio frequency, RF & wireless communications systems

More training courses

Forthcoming Events

    . . . . More Events is operated and owned by Adrio Communications Ltd and edited by Ian Poole. All information is © Adrio Communications Ltd and may not be copied except for individual personal use. This includes copying material in whatever form into website pages. While every effort is made to ensure the accuracy of the information on, no liability is accepted for any consequences of using it. This site uses cookies. By using this site, these terms including the use of cookies are accepted. More explanation can be found in our Privacy Policy