ESD circuit and PCB design guidelines

- a tutorial or summary about ESD circuit and PCB design guidelines and how circuits and PCBs may be designed to withstand ESD.

The need for ESD protection and design guidelines for ESD for electronics devices and electronics assemblies has never been greater. With the geometries within integrated circuits becoming much smaller, they have become much more susceptible to damage from ESD. In addition to this other components like capacitors and resistors that were traditionally not treated as static sensitive devices, SSDs have now become so small that they also need to be treated in the same way.

While manufacture, repair, servicing and maintenance need to be undertaken in a static free environment, part of the ESD protection can be incorporated into the design of the electronics equipment. Implementing ESD design guidelines into the circuits themselves will help make them more robust. Not only will this help during the manufacturing stages when sub-assemblies are exposed to any static that may be in the environment, but when in use, equipment must be able to withstand the levels of static that appear in everyday life.


ESD protection requirement

With electronics devices used in today's electronics equipment being susceptible to electrostatic discharge, it is necessary to employ ESD design guidelines that ensure that devices used will be protected against its effects. The ESD design guidelines and the protection used is of particular importance where any connections are on the periphery of the equipment and may be accessed via the user.

When accessing external ports, users will not take any precautions against ESD, if they even understand about it. Therefore it is necessary to provide full protection for any external ports that may exist.

Electronics devices manufactured today are often required to survive a discharge of 8kV contact discharge (i.e. where the 8 kV is discharged directly onto the pin via a metallic contact) or a 15 kV air discharge (where the 15 kV point is close to the pin and discharges across an air gap). While this is the aim, not all devices will survive this and in many cases the discharge may be greater than this. It is therefore wise to add additional protection.


ESD design methods

The key to the ESD design guidelines for protecting the devices on any external Input / Output (I / O) lines, is to prevent the voltage rising above a level that will damage the interface device. This may be achieved using a circuit that clamps the maximum voltages to just outside the maximum operating extremes. Typically this may be just above the rail voltage and just below the zero volt line.

A typical circuit that can be used for clamping voltages employs reverse biased diodes from the input line to the voltage rail and to ground. This ESD protection circuit must ensure that the voltage excursions on the input line are limited. The diodes must also have a low level of residual current, and the capacitance must be low to ensure that the frequency response / data rate and other input parameters are not impaired.

Diodes used for ESD protection

Diodes used for ESD protection

The operation of the circuit is very simple in that the diodes, D1 and D2 are reverse biased under normal operating conditions. However if a pulse occurs that raises the input voltage above the rail voltage the top diode, D1, will conduct. Similarly if the voltage falls below the ground voltage, the other diode, D2, will conduct. Using ordinary signal diodes, the maximum voltage excursions that might expected on the input line in the first analysis may be +0.5V above the rail and -0.5V below ground. However this is not always the case as seen below.

The typical response curve for an electrostatic discharge is defined by IEC61000-4-5 and it simulates a typical electrostatic discharge curve. The waveform has a rise time of about 1 ns and the current level peaks at 30A. To suppress these voltages, very effective clamping circuits are required and ESD design guidelines need to specify acceptable components and performance limits.

IEC61000-4-2 pulse waveform

IEC61000-4-2 pulse waveform

To provide an approximation to the clamping voltage of a diode the clamping voltage can be approximated as follows:


Vclamp     =     Vconduction     +     (Rdynamic     x     current)


It can be seen that the clamping voltage is related to both the conduction or breakdown voltage (dependent upon the type of diode used) and also the dynamic resistance of the diode. With the very high instantaneous currents exhibited by electrostatic discharges, even very low values of inductance will mean the dynamic resistance is high enough to mean that excessive voltages will appear on the interface lines. Even with DC clamp voltages of around 5V and fast switching diodes, voltages appearing on the device terminals from an electrostatic discharge may exceed 100V. The clamp circuit will have limited the discharge but not to the extent anticipated. In many cases this will be sufficient because of the short duration of the pulses, and the circuits may survive

It is therefore necessary to optimise the circuit to provide the required level of protection.


ESD PCB design

Apart from correctly designing the circuit itself for ESD suppression, the printed circuit board PCB design and layout is also very important. Effort invested in ensuring the PCB design meets the requirements for ESD suppression will save costly debugging later and will also improve the overall reliability of the final equipment as ESD problems will manifest themselves less.

There are a few basic design guidelines for ensuring that any printed circuit board, PCB design is able to reduce problems from ESD to the minimum:

  • Remove circuit loops:   Loops in a line can give rise to unwanted current arising from induction. While this will degrade the performance from general unwanted pickup, it is also important for ESD protection because unwanted current spikes (and hence voltages) can be induced into any loops. Care should be taken to ensure that no loops exist.
  • Utilise ground plane layers in the printed circuit board :   One way of reducing ground loops is to use a ground plane within the printed circuit board. This will enable any signals to be grounded effectively as well as reducing the possibility of ground loops.
  • Reduce line lengths:   Any wire will act as an antenna. With the very short rise times exhibited by ESD pulses, any antenna has the capability of receiving high voltage spikes. By reducing line lengths, the level of radiated energy that is received will be reduced, and the resulting spikes from electrostatic discharges will be lower.
  • Reduce parasitic inductance around protection circuits:   Many electronics circuits will incorporate ESD protection circuits. These can only be effective if the levels of parasitic inductance are low. Parasitic inductance arising from the PCB design can be reduced by keeping line lengths in this area particularly short, and also increasing the track width.
  • Avoid running sensitive tracks near the extremity of the PCB:   As levels of pickup from static discharges are likely to be greater closer to the extremities of the board, it is wise to keep any sensitive lines away from these areas. Input and output lines will often need to reach the PCB edge at some stage, but they can be routed away from the edge as soon as possible where applicable.

Applying the correct ESD circuit design and ESD PCB design guidelines to an assembly will enable it to be resilient to and discharges that may occur. It will also enable the finished unit to pass any ESD testing that may be required for overall certification and marking, e.g. CE marking, that may be needed for it to be sold on the open market. Applying ESD design guidelines at the earliest stages enables the project to be completed in the earliest way without expensive redesign and rework.

By Ian Poole


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