An Applications Specific Integrated Circuit (ASIC) with fully tailored silicon continues to offer the best performance and lowest power dissipation for a high-end System on Chip (SoC). However, the increase of design cost to create a unique, customized solution in technology nodes of 28nm and beyond is a dominating factor. This pushes ASIC technology towards high-volume and high-complexity SoC designs. Less demanding and lower volume applications rely on Field Programmable Gate Arrays (FPGA) that use a different ROI model.
FPGAs are based upon a pre-defined silicon platform that is sold to a broad range of customers. As they are configured by software, the design costs are low. However, FPGA devices require a larger silicon area to implement the same logic complexity. The cost for their development and Intellectual Property (IP) are embedded in the unit price giving FPGAs a significantly higher unit price than comparable ASICs. Reduced computational performance and higher power dissipation limits the FPGAs to low-volume applications with moderate computational requirements in non-power-critical environments.
The gap between ASIC and FPGA technology is making it increasingly difficult to select a solution for mid-volume custom SoC projects. Using an ASIC means accepting substantial design costs, project risks and long implementation times but delivers a low power, low unit price solution. Using an FPGA enables full flexibility and short implementation times alongside much higher unit prices and increased power dissipation. This may turn into a severe commercial issue when mass production volumes increase; reducing the Bill-of-Material (BoM) costs usually means migrating to a prohibitively expensive ASIC solution.
Sitting between ASICs and FPGAs, Toshiba’s Fit-Fast Structured Array (FFSA™) technology for example offers an alternative for custom SoC devices, featuring ASIC-like computational performance with low power dissipation, reduced design cost and affordable unit prices. By using FFSA, traditional ASIC applications benefit from reduced design cost and rapid turn-around times whereas traditional FPGA applications benefit from low power dissipation and lower unit price.
SoC designers may start their design with FPGA devices using Toshiba's IP portfolio and, as production ramps up, easily map the FPGA design to FFSA, requiring no software modifications. The FFSA device can be assembled into an FPGA pin-compatible package to re-use existing PCBs or into a pin-optimized package to achieve cost reduction. FFSAs can later be migrated to fully tailored ASICs to optimize the unit prices for high-volume production, re-using the same software proven by the FPGA and the FFSA devices.
FFSA uses pre-defined and pre-manufactured base layers including design elements for random logic, memories, mixed-signal IP, multi-purpose I/O and high-speed transceivers. The individual FFSA device is personalized by only few metal layers forming standard cell logic, single- or dual-port SRAM, ROM, mixed-signal IP such as PLLs and DLLs, I/O pad cells and high-speed transceivers supporting interface protocols as required.
Being completely configurable by only few metal layers makes FFSA a perfect choice for platform solutions. A complete change of the device functionality is realized within weeks, at only fractions of the costs of a comparable ASIC re-spin. This platform concept is especially suited to storage, networking, IoT, industrial and digital imaging products allowing a quick and low-cost customization for specific applications.
28nm FFSA devices feature up to 54 million gates of random logic and 74Mbit of SRAM. They operate up to 1000MHz providing a maximum of 56 channels of high-speed transceivers running at 12.5 Gbps. Devices with 28 Gbps high-speed transceivers will be available in late 2017. 16nm FFSA devices are planned for 2018 while the roadmap continues to 7nm FFSA devices, due by 2020.
Similar to an ASIC, the random logic inside an FFSA device is realized with a standard cell library consisting of over 500 highly optimized base cell elements. Clocks are distributed throughout the device by real clock trees individually synthesized for each specific design. Using such methodology results in ASIC-like logic speed that is far in advance of FPGA devices, allowing 28nm FFSA devices to operate at similar or higher speeds than 16nm FPGA devices.
In deep-submicron technologies, static power dissipation is the major power driver, especially for FPGAs that use SRAM to store both the configuration and the application data. These memories are always powered-on, causing a constant leakage current. FFSA devices do not need any SRAM for logic configuration and only power on memories as required, leading to a drastically reduced power dissipation. Recent FPGA to FFSA migration projects have achieved power reductions of a factor of 2 or more.
The Toshiba FFSA technology is not only limited to pre-defined masters, but can be embedded into a fully tailored ASIC with a custom floorplan and die size. Used in this way, the technology provides completely new options for SoC development and project risk mitigation. Such FFSA+ devices allow designers to implement mature and proven design blocks including CPU subsystems in the device’s ASIC standard cell area. Non-mature design blocks or design blocks that may change are implemented in the device’s FFSA area, significantly reducing the NRE for a product derivative.
An FFSA+ device with its unique combination of ASIC and FFSA design elements is definitively the best choice for cost-sensitive platform products targeting middle- to high-volume mass production. It will reduce the ASIC project risk tremendously while providing completely new design capabilities enabling fastest product time-to-market.