13 Mar 2011

New IJTAG Standard for Embedded Test

Al Crouch, Chief Technologist, Core Instrumentation for ASSET InterTech outlines the new International JTAG, IJTAG standard.

For many years now, chip makers have routinely embedded test and measurement functionality into their high-end, high-speed devices. This was done out of necessity by the chip makers. They had found that this was the most effective and cost-efficient way to characterize, validate and test their devices.

Now, these high-end chips are entering the mainstream. As a result, the industry is realizing that there is a great wealth of test and measurement, and design-for-test (DFT) intellectual property (IP) embedded on-chip that can be put to good use in a wider range of applications to more cost-effectively validate, test and debug chips, circuit boards and systems throughout their entire life-cycles. The new IEEE P1687 Internal JTAG (IJTAG) standard, which should be ratified later this year, is a step in this direction.

In the Beginning ...

Like many standards bodies, the IEEE P1687 committee was intent on specifying a standard that met the real needs of the industry. In fact, before it was designated a standards committee, the IJTAG working group polled the industry extensively to determine the perceived deficiencies of existing standards that pertained to embedded instrumentation, such as the IEEE 1149.1 boundary scan (JTAG) standard and the IEEE 1500 core test standard. In a very real sense, the five years of work that's been invested in developing P1687 has been a long and involved response to the group's original findings concerning the needs of the industry.

One of the primary objectives of the IJTAG committee was to streamline how embedded on-chip instruments functioned by defining a standards-based interface for these instruments. The committee believed that this would simplify the task of using these instruments and a standard instrument interface would create an opportunity for the development of a third-party marketplace for tools that would complement this IP. In addition, committee members felt that eventually a market for portable third-party embedded instrumentation could develop.

To complete a first version of the IEEE P1687 IJTAG standard, the committee borrowed from the IEEE 1149.1 boundary-scan standard. As a result, at least initially P1687 reflects certain architectural features of the boundary-scan standard. For instance, IJTAG re-uses boundary scan's concepts of a Test Access Port (TAP) and controller. Moreover, the IJTAG access network for embedded instruments incorporates a set of registers that is similar to the Test Data Registers (TDR) found in the boundary-scan standard and which typically comprise every boundary-scan chain.

The On-Chip IJTAG Architecture

Although similar, boundary-scan and IJTAG scan chains have several very important differences. For example, boundary-scan chains are fixed in length and composition while IJTAG networks are dynamic and variable in their configuration. In fact, segments in an IJTAG scan chain or network can be added or subtracted as requirements change. Unlike 1149.1 boundary scan which is based on a concept of fixed instructions, the configuration of an IJTAG chain is controlled by the variable data passing through the chain's data registers.

Consequently, the IEEE P1687 IJTAG standard is flexible from an architectural standpoint. Designers can deploy various configurations of an IJTAG network in order to meet a wide range of engineering, cost, operational and other tradeoffs. These architectural configurations are documented by defining them in the IJTAG standard's Instrument Connectivity Language (ICL). ICL essentially describes where the IJTAG TDRs are, the scan paths that connect and access them, how and when these scan paths should vary, the connections between the IJTAG scan paths and the boundary-scan TAP controller on the device, and the parallel connections between the embedded IJTAG instruments and the IJTAG TDRs.

This example of an on-chip IEEE P1687 architecture includes a IEEE 1149.1 boundary-scan TAP controller with its four signals and three instances of 1687's Segment Insertion Bit (SIB) which allows on-demand access to instrument interface registers.

Segmenting the Network

In the IEEE P1687 standard the relative equivalent of IEEE 1149.1 boundary scan's Instruction Register (IR) would be the Segment Insertion Bit (SIB). Instructions to select any given boundary-scan TDR come from the chip's 1149.1 boundary scan TAP Test Controller IR or the Wrapper Instruction Register (WIR) which is defined in the IEEE 1500 core test standard. To create the active chip-level scan chain that includes the TDR associated with an instrument, an instruction encoding would be installed which would connect the selected TDR to the chip's Test Data In (TDI) and Test Data out (TDO) pins. This would allow serial scan data to pass through the chip and by the embedded instrument's internal signals.

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