24 Aug 2015
DDR Memory Characterization Using a Mixed Signal Oscilloscope
Sadaf Siddiqui of Keysight Technologies describes how an MSO can be used for read and write data separation for full DDR design testing, debug, and characterization.
A real-time oscilloscope has always been a powerful tool for high-speed memory designers doing DDR electrical or parametric compliance testing, debug, and characterization.
With the limited channels on a real-time oscilloscope, it can be difficult to trigger on DDR protocol and decode to separate read and write data on the bidirectional data bus. With 16 additional high-speed digital channels, a mixed signal oscilloscope (MSO) enables the designer to probe, decode, and trigger on the DDR command bus to accurately identify read and write cycles.
Why use an MSO?
DDR read/write cycles behaviour: Let’s begin by taking a look at the behaviour of the DDR read and write signals on a limited number of analogue channels. There are ways to identify read and write data on the bidirectional bus by taking a look at the data strobe (DQS) and data (DQ).
Figure 1 shows read and write data of a DDR3. You can see that the DDR3 read and write pre-amble patterns are distinctly different. The read preamble goes from hi-z state to low before the first rising edge of DQS to signal the first read data bit. The write preamble goes from hi-z to high, then low before the first rising edge of DQS to signal the first write data bit. And lastly, DDR3 DQ signal is usually in hi-Z state before transitioning to valid data.
Figure1: DDR3 DQS and DQ
Figure 2 illustrates the behaviour of a DDR4 strobe and data. The DDR4 read and write pre-amble pattern is very similar to each other. DDR4 utilizes the pseudo open drain drivers rather than the push-pull as the DDR3 to reduce current draw. The DQ signal here shows high state rather than the hi-z of the DDR3 between data bursts. This level is tunable or can be turned off and the DQ signal can look different that the nominal setting seen here.
Figure2: DDR4 DQS and DQ
DDR read/write separation methods: When testing and validating DDR designs, one of the biggest challenges that the designer may encounter is separating the read and write data on the bidirectional lines. Figure 3 is a DDR2 signal, which like DDR4, has a similar pre-amble for both read and write. With a simple edge trigger on DQS, the read and write data are overlapped. To make valid electrical and timing measurements, the read and write data needs to be separated. There are multiple ways to separate read and write cycles.
The easiest way to do this is to use a software identification trigger. By drawing a zone on a distinctive burst pattern of read or write, we can separate the read and write data. Figure 3 shows write data being separated out. We know this because write data is generally center aligned, while read data is generally edge aligned.
Figure 3: Software zone triggering
Another method to do read or write data measurement is automated compliance application software. Based on the DQS and DQ relationship, the software would make an educated analysis of the input and output measurement automatically. The common method or algorithm use to do this is through phase alignment of DQS and DQ. The software could also make use of the pre-amble pattern to qualify read and write data.
In DDR3, read and write pre-amble patterns are different so using the pre-amble pattern to separate read and write data makes sense. But for DDR2 and DDR4 having the same pre-amble patterns, and sometimes different behavior of a DDR3 system could cause the software to mistakenly identify a read or a write cycle if the phase difference is not obvious. Figure 4 shows an example of a read cycle where some data is not exactly edge aligned and could be mistakenly identified as a write cycle.
Figure 4: Read data alignment
DDR read/write protocol: While these two methods to separate read and write using only DQS and DQ are valid and useful ways to separate, they do lend themselves to mistakes in separation and ultimately the wrong measurements.
The clearest way to separate read and write data would be to command decode using the DDR command truth table available in JEDEC specification. Before the existence of MSO, this method can only be achieved using a logic analyzer or protocol analyzer. This method requires access to at least 5 command pins, which include, CLK, CS, RAS, CAS and WE. With an MSO, there’re 16 digital channels in addition to the standard 4 analogue channels. An MSO can decode the read/write commands and trigger on the command to see the analogue behaviour of the correspondent DQS and DQ signals via the analogue channels.
For LPDDR technologies, there is also a similar command truth table that can be used for command decode. But instead of RAS, CAS and WE, you would connect to CA0, CA1 and CA2. In LPDDR technology, the address and command signal share the same pin.
Using the MSO to trigger and make measurements?
Protocol Trigger and Search: There are 3 basic steps that you would need to do in order to set up the MSO correctly for DDR decode. First, assign the channels to the right bus. Second, set the voltage thresholds, normally VREF of the signal. Finally, set up optional signals for added decoding.
Figure 5: Steps to setting up protocol trigger and search
Sometimes, the DDR signals have different VREF levels between the command buses. As speed increases, this characteristic becomes very common. You may need to probe the signal on an analog channel to see what the actual voltage swing is to find the optimal voltage reference point. And they may be different depending on the trace lengths or probing that you used and other signal integrity factors.
Figure 6: Measuring signals to verify reference voltage.
The MSO in the market today comes with standard trigger and decode for DDR technologies (DDR2/3/4, LPDDR2 and LPDDR3). The protocol decode menu allows you to assign channels to all the buses that forms a DDR command decode. There are some buses that are required for a command decode, for example, RAS, CAS, WE and CS. If you have access to additional signals, you would get more command options. For example, access to CKE would enable you to decode Power down entry and power down exit commands. Notice that the capability resides in the MSO hardware and there’s no need for setup of symbol files to relate the channels to a command protocol. There’s also an option to decode more buses like address.
Figure 7: Protocol menu
Ultimately, the next thing you want to do with your MSO is trigger on the command. You could either trigger on just a command, or you could do a DQS trigger associated with a read/write command. This trigger feature is what makes the MSO so powerful for DDR debug.
Figure 8: Selecting command to trigger
Next to set up is to trigger on the DQS associated with a read or write command. For example, if we want to trigger on the first valid burst of read, I would use this trigger function along with an input of what the read latency is. Latency is the number of clock cycles from the first valid command to the first valid burst after the pre-amble. We can then align the first bit of read DQS and have it be jitter free for make timing or eye diagram measurements.
Figure 9. Setting up and associating DQS with command trigger
Eye diagram measurement on DQS/DQ: Now that we know we are consistently triggering on write data, let’s do more analysis and make a real time eye measurement. By using the math function of Horizontal Gating, we can specify a specific portion of a burst that we are interested in measuring.
Figure 10: Gating write burst for data eye measurement.
Now we can set up the eye measurement by using the eye diagram wizard with clock being function 1, gated channel 1 of DQS and data would now be function 2 which is the gated function of channel 2, DQ. Eye height, Eye width, and mask measurements can now be made. Figure 11 shows an eye mask measurement and unfolding the eye at a failure to analyze the signal. To do this, set the eye diagram to stop on failure. Once it stops, select unfold eye. We are able to clearly see where the failure is, and analyze and target some specific electrical and timing measurements in that waveform to determine the root cause.
Figure 11: Eye measurement and analysis
As data rates increase, it is more important than ever to accurately analyze and measure read and write data timing. An MSO is a powerful tool to help trigger and pinpoint the signals to be measured and analyzed. These measurements can be done efficiently and accurate.
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About the author
Sadaf Siddiqui is the Global High-Speed Digital Marketing Programs Manager, Electronic Measurements Group at Agilent Technologies. Sadaf has around 12 years of Technical Applications & Marketing Experience, mainly in Test & Measurement, Embedded & Software domain. He possesses good insights into the Test & Measurement domain and various test needs in different segments. He is an active contributor in Electronics and Telecom media for technology and T&M articles. Prior to joining Agilent Technologies, Sadaf Siddiqui has worked as Technical Applications Engineer/Consultant with organizations as Tektronix and Trident Infosol with exposure on High Speed Standards, Embedded Softwares & DSP. Sadaf earned his Bachelor's degree in Electronics Engineering from AMU, India. He received a Post Graduate Diploma in Business Management (Marketing) from Symbiosis Institute, Pune(India).
Keysight Technologies is a leading producer of most types of test equipment for the electronics and other industries. The company was originally included within Agilent before its two elements split in 2014, and before that it was part of Hewlett Packard, HP.
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