16 Sep 2014
Optimizing a Doherty Amplifier with a Monolithic RF Controller
Naveen Yanduru, Ph.D. and Kinana Hussain of Peregrine Semiconductor look at optimising the overall performance of a Doherty amplifier using an RF controller.
Anyone who has been tasked with implementing a Doherty power amplifier (PA) for a wireless base-station transmitter can attest to the difficulties that lie in Doherty amplifier optimization.
There are the manufacturing variances, the manual tweaking of each module, the discrete components and their own variances, not to mention the lack of flexibility after optimization. For an engineer, it is a time-consuming challenge—time that is also an investment cost for the company.
Doherty amplifier advantages
Despite these challenges, the Doherty amplifier continues its dominance in the wireless infrastructure equipment market. Why? The answer lies in the amplifier’s ability to accommodate high peak-to-average ratios (PAR).
With the advent of amplitude modulation in wireless and the worldwide rollout of LTE, the PAR required can be as high as 9 dB. A Doherty configuration uses load modulation to allow for very high efficiencies to be achieved under back-off conditions.
The back-off efficiencies are the key to keeping the overall system efficiency of the PA module high for LTE signals. Most wireless base stations implement a Doherty architecture as a way to improve PA efficiencies, especially when amplitude modulations are involved.
For those unfamiliar with Doherty PA’s architecture, the amplifier has a dual-path architecture that consists of two amplifiers—a carrier amplifier and a peaking amplifier, as shown in Figure 1. Invented in 1936, the Doherty’s two amplifier paths enable a significant efficiency gain over traditional architectures. The carrier amplifier is a class AB amplifier designed for carrier signals. The peaking amplifier is a class C amplifier optimized for high peaks in the signal. Signals enter through a main RF input and are then split into zero- and 90-degree phases before they run through the carrier and peaking paths within the amplifier. At the end, the signals are combined to form the output signal.
The architecture has an output-combining network, allowing for the carrier amplifier to see a higher impedance and thus experience higher voltage swings under back-off conditions. By showing a higher impedance to the carrier amplifier under these conditions, the carrier amplifier uses the available voltage headroom and works closer to saturation. A Doherty amplifier also keeps the class C peaking amplifier turned off under back-off conditions. As the power starts moving towards the peak power, the peaking amplifier turns on and the output Doherty network experiences load modulation. The carrier amplifier then sees a lower impedance than the high impedance it was presented in back-off conditions.
Figure 1: A Doherty power amplifier has a dual-path architecture that consists of a class AB carrier amplifier and a class C peaking amplifier.
Doherty amplifier optimization challenges
In a Doherty configuration, there are multiple components that make the amplifier both frequency and manufacturing sensitive. The output load-matching transformer is a quarter wave transmission line section with 35-Ohm characteristic impedance. The impedance inverter between the carrier and peaking amplifier is another quarter wave transmission line section with 50-Ohm characteristic impedance. Both of these transformers are frequency sensitive, along with the output matching networks of the peaking and carrier amplifier. Additionally, the offset lines, which are used to optimize the impedance at the output of each amplifier, are also frequency sensitive.
When the peaking amplifier is off under back-off conditions, the offset lines at the output are used to rotate the output impedance towards open circuit. This allows for the peaking amplifier to be invisible to the carrier amplifier. If the offset lines are not perfect, the carrier is presented with a finite impedance from the peaking, which compromises the Doherty amplifier’s performance. The output impedance of the peaking amplifier when it is switched off is sensitive to manufacturing variances. When the offset line is not right, it compromises the high impedance back into the peaking amplifier and reduces the Doherty performance by negatively impacting the optimum balance between output power, efficiency and linearity. More often than not, an engineer must manually tweak each module, compensating the phase at the input of the peaking amplifier for any non-idealities and manufacturing variations in the implementation of the Doherty amplifier.
If the carrier and peaking amplifier are not in sync, then the final output will not reach the output performance as designed. Today, most macrocell RF engineers manage this complexity using discrete components to tune the phase and amplitude for each one of the carrier and peaking paths. But discrete components come with their own set of manufacturing variances. For example, O4O2 or O6O3 surface mount components can easily vary, especially on the lower values of capacitance. Even if the engineer is using some kind of transmission line-based matching network, capacitance values can vary by up to 20-percent. The same is true with any micro-strip layers. As the engineer optimizes the amplifier for higher bandwidths, these variations eat into the margins and make the Doherty even more susceptible to manufacturing variations, given its propensity to be frequency sensitive already.
Using discrete components is a proven methodology, and it keeps the bill of materials (BOM) low because discrete components are cheap. On the other hand, the methodology requires substantial engineering time and expertise because optimization is both manual and laborious. Engineers must determine what the discrete component values are and how they need to be put on the board. Furthermore, once the discrete components are on the board, there is no flexibility to make changes for unexpected power-transistor variances. The RF engineer is left with no way to optimize the phase and amplitude.
Any mismatch or misalignment in phase and amplitude between the Doherty architecture’s carrier and peaking paths can quickly contribute to higher costs and degradation of the overall performance. These problems are compounded in asymmetric Doherty architectures. With a smaller carrier-path PA and a larger peaking-path PA, it is more complex to align the two paths. Path misalignment contributes to a reduction in the overall PAE, a reduction in the effectiveness of the digital pre-distortion (DPD) loop, and a reduction in Doherty PA yield.
UltraCMOS MPAC solves the Doherty optimization challenge
Aware of the challenges Peregrine’s customers had to endure to put Doherty amplifiers into production, Peregrine sought to create a solution to this RF challenge. At the International Microwave Symposium (IMS) in June 2014, Peregrine introduced a solution—a monolithic RF controller. UltraCMOS MPAC (monolithic phase & amplitude controller) enables alignment of the phase and amplitude between the Doherty amplifier’s carrier and peaking paths through a digital interface.
On an UltraCMOS chip, each MPAC product (Figure 2) includes:
90-degree hybrid splitter
Two phase shifters
Two amplitude controllers
Digital serial peripheral interface (SPI)
Figure 2: UltraCMOS® MPAC (monolithic phase & amplitude controller) enables alignment of the phase and amplitude between the Doherty amplifier’s carrier and peaking paths through a digital interface.
Built on Peregrine’s UltraCMOS technology, MPAC independently adjusts the phase and the amplitude on the carrier and peaking paths. The single-chip system, which features a digital SPI, also integrates a 90-degree splitter with relatively flat phase split across the frequency band that otherwise would have been a discrete component. For each one of the different paths, MPAC offers engineers maximum flexibility in adjusting the phase and the amplitude, allowing them to tune the carrier and peaking paths through the SPI.
With a wide phase shift range of 87.2º and a fine step size of 2.8º per path, MPAC delivers high linearity of 65 dBm IIP3 and extremely low power consumption of 300 µA. In addition, it can support 31dBm of peak input RF power and has high port-to-port isolation of 30 dB. As MPAC is built on an UltraCMOS monolithic die, RF engineers can trust the industry-proven uniformity and manufacturing reliability of the UltraCMOS process. Additionally, UltraCMOS technology enables superior ESD performance of 1 kV, an extended temperature range up to 105-degree Celsius and a wide power supply range from 2.7 to 5.5V.
With a 4-bit attenuation code sweep at 0.5 dB LSB (least significant bit), MPAC has low reference insertion loss, has good attenuation error accuracy and is monotonic for the entire frequency band, as shown in Figure 3.
Figure 3: MPAC’s single path relative attenuation (includes –3 dB loss from hybrid splitter) maintains low attenuation error and monotonicity across the entire frequency range.
With a 5-bit phase code sweep at 2.8º LSB, MPAC’s single path relative phase has good accuracy and maintains monotonicity across the entire RF frequency range, as shown in Figure 4.
Figure 4: MPAC’s single path relative phase maintains monotonicity across the entire RF frequency range.
Beyond Doherty amplifiers, MPAC can be used in optimizing performance for other dual path, dynamically load modulated amplifier architectures, such as LINC and Chireix amplifiers. Additionally, MPAC can be utilized for vector generation purposes in feed forward amplifiers, beam-forming networks and dual polarized alignment/generation applications.
Advantages of Adding UltraCMOS® MPAC to Transmit Line Up MPAC eliminates the need for multiple discrete components and enables wireless-infrastructure vendors to improve system performance, lower cost, improve the overall product reliability and deliver maximum tuning flexibility for either LDMOS (laterally diffused metal oxide semiconductor) or GaN (gallium nitride) based Doherty power amplifiers.
1) Improved system performance: MPAC can significantly improve the overall power added efficiency (PAE) and linearity across the frequency range and the Doherty bandwidth. If a company is not already investing in module-by-module tuning, then engineers can expect to see an up to three to four percent efficiency increase—a huge improvement.
2) Lower cost: Wireless infrastructure vendors using MPAC can benefit from the reduced energy costs, reduced BOM costs and reduced engineering and manufacturing costs.
3) Improved reliability: MPAC increases the yield of power amplifier sub-assemblies and improves uniformity and repeatability between transmit paths.
4) Maximum tuning flexibility: Through the digital interface, MPAC gives engineers the maximum flexibility to adjust the phase and amplitude for each one of the different paths. There is the flexibility to actively tune for operational and environmental factors.
MPAC and the advantages it offers the industry could not have come at a better time. The LTE market is exploding, yet the industry has only explored the tip of the LTE iceberg. According to Ericsson’s mobility report, LTE networks covered 20-percent of the world’s population in 2013 with that number projected to grow to more than 65-percent by 2019. In order to accommodate the projected 10x growth in mobile data traffic during that same time period, the density of LTE networks is increasing exponentially. As the world continues to rollout LTE and LTE-A, Doherty amplifiers are challenged to achieve power efficiency with wider bandwidths and greater PARs.
Currently being sampled to select customers, the PE46120 is the first product in the MPAC family and covers a frequency range of 1.8 to 2.2 GHz.
The market needs solutions that improve the Doherty’s phase and amplitude precision, maximize performance, lower costs and deliver tuning flexibility. Peregrine Semiconductor answered the industry’s call with UltraCMOS® MPAC—a monolithic RF controller. Now, it’s time to see if MPAC will solve the Doherty amplifier optimization challenge for engineers.
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About the author
Naveen Yanduru, Ph.D is the vice president of product development at Peregrine Semiconductor. Before joining Peregrine in 2011, he held engineering and management positions at Samsung Telecommunications and Texas Instruments. Naveen earned his Ph.D. in electrical engineering from the University of Texas at Dallas.
Kinana Hussain (pictured) is the senior marketing manager at Peregrine Semiconductor. He previously held multiple positions in engineering and management at Vitesse Semiconductor. Kinana earned an MBA from UCLA Anderson School of Management and a bachelor of science in electrical engineering from Cal State University, Northridge.
Peregrine Semiconductor (NASDAQ: PSMI) is a leading fabless provider of high-performance, integrated RF solutions and the founder of RF SOI. Peregrine’s UltraCMOS® technology – a patented, advanced form of SOI – delivers the performance edge needed to solve the RF market’s biggest challenges.
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