18 Nov 2014
Design of 15 GHz GaN MMIC Power Amplifiers
Stuart Glynn, Tony Richards, Liam Devlin of Plextek RF Integration investigate the design of gallium arsenide MMICs at 15 GHz for line of sight link applications
GaN, gallium nitride, technology has a well-proven capability for the realisation of solid state power amplifiers, SSPAs, especially those requiring very high levels of saturated output power.
As the technology has matured it is increasingly used in a wider range of applications, including many commercial communications applications requiring high linearity to preserve modulation fidelity.
Most power amplifiers, PAs, currently used in point-to-point microwave link applications are based on GaAs PHEMT technology, but GaN is now also a contender for this application. However if GaN solutions are to be adopted, they need to provide a performance advantage at a comparable cost.
This paper considers the design and analysis of a GaN MMIC PA for the 15GHz point-to-point link band, targeting the outline performance specification in Table 1. The initial design was optimized for IP3 - the traditional microwave measure of linearity for amplifiers. The performance when amplifying QAM 256 modulated signals was then analyzed. Spectral re-growth and Adjacent Channel Power Ratio (ACPR), distortion of the constellation and Error Vector Magnitude (EVM) were all evaluated.
|Table 1 Target Specification for 15GHz GaN PA|
|Frequency Range||14.5 to 15.35GHz|
|OIP3||45dBm at 22dBm per output tone|
|Chip Area||<< commercially available GaAs parts|
The design used Cree’s 0.25µm GaN-on-SiC process biased at 28V Vds, which is capable of delivering 4W of RF output power per mm of gate width. A layout plot of a 4-gate finger transistor is shown in Figure 1. The use of inter-source vias (positioned beneath each source finger) helps keep the source inductance low and along with the wide gate spacing provides improved thermal performance.
Figure 1 Layout of 1mm device from Cree’s 0.25um, 28V, GaN on SiC process
The high power density of GaN transistors means that careful attention to thermal performance is vital to ensure adequate reliability for the resulting amplifier. The transistor models in the Cree Process Design Kit (PDK) are able to predict junction temperature and account for the thermal effects on RF performance. To do this they require a value for the baseplate temperature (Tbase) and the thermal resistance (Rth) of the transistor from junction to baseplate. The overall thermal impedance must be determined by the designer, and this will vary significantly with the baseplate temperature as the thermal conductivity of SiC reduces by a factor of 2.5 between 25°C and 200°C.
Preliminary simulations were made to select the preferred transistor size and bias point, and to determine the most appropriate amplifier topology. Figure 2 shows a plot of the maximum available gain (Gmax) versus frequency for a 4x250µm transistor (1mm total gate width) biased at 28V Vds and 100mA Ids. The deflection in the Gmax curve at around 12.5GHz corresponds to the transition between the lower frequency region of conditional stability and the region of unconditional stability (K > 1) above this. At 15GHz Gmax is around 14dB. Allowing for implementation losses (matching networks, bias circuitry, gain flattening and low frequency stabilising networks) should still yield a gain of 11 to 12dB per stage in the operating band.
Figure 3 S22 plot of 1mm device biased 100mA from 28V
An analysis of the device S22 (Figure 3) suggests that conjugate matching to 50Ω can be conveniently achieved by the addition of a shunt inductor close to the drain. A shunt inductor of around 0.3nH would transform the impedance indicated by Marker 1 to the centre of the Smith Chart. This is a benefit of the high voltage operation of GaN, which results in power transistors with a much higher output impedance than comparable devices on competing technologies.
Figure 3 S22 plot of 1mm device biased 100mA from 28V
The next step in the design process was to undertake large-signal load-pull simulations. For this application, linearity is more important than saturated output power performance. The optimum load impedance was determined for maximum Psat (saturated output power) at 15GHz, and load impedance contours were plotted as the input power was varied (Figure 4).
Figure 4: Output power load pull contours of 1mm device biased at 100mA Ids, 28V Vds
The maximum saturated power delivered to the load is just over 4W (36.2dBm); at this stage no allowance for output matching, combining or biasing networks has been made. A similar set of contours was also produced for Power Added Efficiency (PAE), shown in Figure 5, indicating a maximum PAE for the single transistor of 46.8%. The two optimum impedances for these two cases are not far apart, which is a useful feature of the process.
Figure 5: Power added efficiency load pull contours of 1mm device biased at 100mA Ids, 28V Vds
For the application under consideration, linearity is more important than saturated output power performance. Large-signal analysis was therefore undertaken with two input tones of a specified level, and the load impedance for optimum intermodulation performance was determined. This is shown in Figure 6, where the different contours illustrate the degradation in intermodulation performance as the load impedance moves away from the optimum. At the optimum impedance point the two output tones are each +18dBm, so the -50.2dBm third-order product level gives an OIP3 of +43.1dBm.
Figure 6: Third order intermodulation load pull contours of 1mm device biased at 100mA Ids, 28V Vds
The imaginary parts of the optimum load in the large signal analyses presented above is very similar in each case, and can be implemented by the use of a shunt inductor close to the drain of the transistor. This inductive matching component essentially resonates with the Cds of the transistor. The remaining real impedance seen by the device is 48Ω for optimum Psat performance, 70Ω for optimum PAE and 140Ω for optimum linearity.
Detailed Amplifier Design and Layout
Based on this preliminary simulation work, it was decided to implement a two-stage amplifier design based on two output transistors each of 1mm gate width together with an input driver stage to provide the overall level of small signal gain.
It is important that the input stage is large enough to drive the output stage without exhibiting excessive compression. GaN transistors have high gain, but it is a mistake to use too small a driver stage as the soft compression characteristics of GaN mean that the driver stage and output stage will compress simultaneously, causing the amplifier linearity to be compromised.
The shunt inductors used for load matching are RF grounded, which provides a convenient place to which the drain bias can be applied. RC decoupling is also included at this point as a convenient means of adding low frequency attenuation and ensuring broadband stability. A transmission line transformer is used to combine the RF power from the two output transistors. Gate bias is applied via a high impedance transmission line, which is meandered to save die area.
As with the drain bias, RC decoupling is applied to improve low frequency stability. A low-pass inter-stage matching network is used to transform the output impedance of the first stage and to split the signal to drive the two output devices. The nominal quiescent bias current of the complete amplifier was increased slightly during the detailed design and optimisation, from the initial 100mA/mm to 130mA/mm. A layout of the complete two stage amplifier is shown in Figure 7.
Figure 7: Layout plot of the two-stage GaN PA MMIC
Figure 8 shows how the layout of the complete 15GHz amplifier compares with a commercially available GaAs part with similar linearity performance. The thick blue box indicates the outline of the GaAs part. Not only is the GaN die smaller, its linearity is also 2dB higher. This clearly demonstrates the potential benefit of GaN technology for line-of-sight applications.
Figure 8: Comparison of die area of 15GHz GaN PA MMIC and outline of commercially available GaAs part of similar linearity (blue box)
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About the author
Stuart Glynn began his career at Matra Marconi Space in 1997 after graduating from UMIST. Mooving to Sony he later moved on to Nanotech Semiconductor, later joining Plextek,in 2009 becoming a member of the RF Integration Group, which became a separate line of business in November 2012.
Tony Richards graduated from Loughborough University of Technology in 1977 and joined Pye Telecommunications Ltd, later moving on to Philips Research Labs in Eindhoven later returning to Philips in the UK. In 1999 he joined Plextek, becoming a member of the RF Integration Group, which became a separate line of business in November 2012.
Liam Devlin graduated from Leeds University in 1988. After working for Philips and GEC, he joined Plextek, in 1996 becoming a member of the RF Integration Group, which became a separate line of business in November 2012. He has been involved in the design of over 80 custom ICs on a range of GaAs, GaN and Si processes at frequencies from baseband to 90GHz. He has published over 40 technical papers in peer reviewed journals and conferences. Liam is also a non-executive director of Interlligent UK.
Plextek RF Integration is a UK-based design house specialising in the design and development of RFICs, MMICs and microwave/mm-wave modules. We have designed over 80 custom ICs at frequencies ranging from baseband to 100GHz and are a third party design house for Cree, GCS, TriQuint and WIN. Our designs are used in a wide range of applications from test instrumentation to infrastructure equipment and very high volume consumer wireless devices. We have in-house test facilities for both bare die (RFOW) and SMT packaged components. Our microwave and mm-wave module development activity encompasses a wide range of technologies including conventional SMT on laminate substrates, High Density Interconnect (HDI), chip and wire, thin film, thick film and LTCC. Plextek RF Integration is part of the Plextek Group.
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