23 Nov 2015
Heterogeneous 3D System-in-Package Integration
Manish Deo, Altera Corporation highlights the process technology considerations when designing devices to meet the constantly increasing demands for throughput.
Next-generation platforms are evolving rapidly to keep pace with emerging system trends driven by an explosion of applications such as data centre capabilities, Internet of Things, IoT, 400G to terabit networking, optical transport, 5G wireless, 8K video, etc.
The resulting expansion of connectivity and processing will affect the semiconductor space significantly, from the type of components that are built to higher efficiency systems and related services. A close evaluation of this emerging landscape reveals some interesting trends.
For example, next-generation data centre workloads demand increasingly higher computational capabilities, flexibility, and power efficiencies; outstripping the capabilities of today’s general-purpose servers. Additionally, data centre infrastructure must be virtualized and delivered as a service over commodity servers to reduce complexity and provide greater business agility and scalability.
However, server performance improvements have actually slowed, primarily due to power limitations. Designing data centre solutions for specific workloads increases efficiency but significantly limits the homogeneity and flexibility of the solution. Flexibility is crucial because data centre services evolve rapidly and require adaptable hardware.
IoT reflects similar challenges. IoT is projected to grow dramatically and hit the multi- billion “smart objects” mark in the near future. These smart objects are connected and communicate with each other or to a cloud or data centre. The infrastructure must determine which data needs to be processed and which data is dropped, all in real time. Therefore, IoT requires a highly connected, flexible, efficient, bandwidth-rich infrastructure that enables insight from the data centre to the edge. This requirement challenges service providers, data centres, cloud computing, and storage systems to satisfy this insatiable demand for Internet traffic.
Next-generation platforms reflect a common underlying theme: the need for increased bandwidth and functionality with lower power profiles and footprint requirements. Simply put, the devices used to build these next-generation platforms must do more, be faster, take less printed circuit board (PCB) real estate, and burn less energy, all at the same time. This challenge requires innovative solutions across the semiconductor ecosystem.
Thus, system architects designing next-generation platforms must try to meet the requirements of achieving a higher bandwidth, lower power consumption and a smaller footprint. There is also the need to increase overall device functionality and flexibility.
Historically, system architects have responded to these requirements by packing more discrete components on a standard PCB, attempting to provide maximum functionality and performance while keeping power budgets in check.
This conventional integration scheme is nearing its logical end as it struggles to keep pace with-next generation requirements. Some of the key challenges are:
Chip-to-chip bandwidth limited by the interconnect density permitted by underlying PCB.
System power is too high due to the need to drive long PCB traces between components.
Form factor is too big due to the number of discrete components required for the desired system functionality.
System architects have looked at monolithic integration for some components to address these limitations. However, this integration leads directly to another challenge: IP maturity. Different IP blocks mature at different process nodes, and by extension are available at different times. Therefore, it is not possible to integrate all desired IP blocks or functionality monolithically. For example, if a vendor is building a logic die using 14 nm technology and wants to integrate DRAM on chip, the only option is DRAM built using 40 nm or older technology. This limitation does not facilitate a monolithic solution.
Another key challenge is the need to provide maximum high-speed connectivity between devices. However, many of the protocol standards continue to evolve and the required data rates and modulation schemes from system-to-system vary. Thus, it is imperative to define an innovative solution that integrates emerging technologies and IP blocks quickly.
The challenges posed by next-generation systems have begun to define the solution landscape. Conventional solutions cannot meet the requirements of the future: higher bandwidth, lower power, smaller form factor, and increased functionality and flexibility. The challenge is to develop an innovative, commercially viable, scalable solution that meets these requirements.
One recent announcement from Altera introduces a heterogeneous 3D system-in-package (SiP) technology is believed to addresses all of these challenges: higher bandwidth, lower power, smaller form factor, and increased functionality and flexibility. The in-package integration is scalable and straightforward to manufacture.
Heterogeneous 3D SiP technology allows various components to be integrated alongside an FPGA into a single package to match system requirements, effectively providing robust solutions more quickly than in previous generations [Figure 1]. This approach enables in-package integration of a range of components such as analogue, memory, ASIC, CPU, etc.
Figure 1: FPGA-based Heterogeneous In-Package Integration
The approach to heterogeneous 3D SiP integration is unique in the FPGA industry in that it uses a single monolithic FPGA core fabric (up to 5.5 million logic elements) and integrates multiple die around the FPGA. A monolithic FPGA core fabric provides maximum performance and utilization, and ensures that data can be processed at the highest rates possible without running into routing congestion, utilization bottlenecks, or degraded performance.
The technology that makes broad deployment possible is Intel’s patented, Embedded Multi-die Interconnect Bridge (EMIB). Intel designed EMIB for solutions that require advanced packaging and test capabilities. EMIB provides a simple integration flow and offers an ultra-high-density interconnect between heterogeneous die in the same package. It also enables in-package functionality that was either too complex or too cost prohibitive to implement with alternative in-package integration solutions.
The EMIB technology offers a simpler manufacturing flow, higher performance, enhanced signal integrity, and reduced complexity.
EMIB is a small silicon chip embedded in the underlying package substrate and offers dedicated ultra-high-density interconnect between die. The EMIB flow does not use any through silicon vias (TSVs), which significantly reduces manufacturing complexities while improving signal and power integrity metrics.
Importantly, the EMIB physical dimensions do not limit the number of die that can be integrated. In contrast, alternative implementations use a large piece of silicon interposer that sits on top of the package substrate and exceeds the entire length of the die to be integrated. The large piece of silicon interposer makes the solution cost prohibitive and prone to issues such as warpage, etc. Alternative solutions also require a large number of micro bumps using micro vias, which affects the overall yield and manufacturing complexity. Additionally, the number of die that can be integrated using an interposer is limited, affecting the scalability. [Figure 2]
Figure 2: EMIB Implementation vs. Alternative Interposer-based Implementations
Next-generation platforms increasingly require innovative solutions that provide significantly higher performance, lower power, and smaller form factors. The explosion in data centre capabilities and proliferation of IoT technologies are emerging as key drivers. In addition, advancements in terabit networking, optical transport, 8K video, and 5G wireless domains are ramping up rapidly, forcing the semiconductor ecosystem to find innovative solutions.
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About the author
Manish Deo, senior product marketing manager, Altera. He is a seasoned semiconductor marketing professional with a proven 12 year track record in FPGA engineering design experience spanning board design, timing verification, silicon validation and methodology development. He has been with Altera for nine years and has a Master’s degree in electrical engineering from the University of Toledo and a Bachelor’s degree in electrical and electronics engineering from Nagpur University.
Altera programmable solutions enable designers of electronic systems to rapidly and cost effectively innovate, differentiate and win in their markets. Altera offers FPGA, SoC, CPLD, and complementary technologies, such as power solutions, to provide high-value solutions to customers worldwide.
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