18 Mar 2017
Modern Power Supply System Design
Ron Wilson of Intel PSG looks at how modern systems require different power supply system design as power supply requirements become more exacting.
Power supply and power distribution design for modern electronic systems is becoming more complex as energy demands at each level, from whole systems to individual ICs, both increase and become more dynamic.
In large systems, such as data centres, the pressure is on to shift from 12 or 24V DC power distribution up to 48V – and extend its reach from the bottom of racks and the backs of chassis towards the key SoCs and CPUs.
At the same time, modern ICs are increasingly demanding power supplies that can offer huge bursts of current, multi-decade operating ranges, fast transients and digital controls. Designing systems for delivering power to the point-of-load, PoL, has become a complex mix of multivariate systemic optimization and high-bandwidth mixed-signal design.
Restructuring the power supply system
Managing power delivery at the system level now involves making a series of hierarchical trade-offs. For example, although 12V, 24V and 28V DC are well established in automotive, data-centre and aeronautical markets, large cloud-computing companies such as Google are experimenting with using 48V DC for bulk distribution. Their design architecture delivers 48V DC to the PoL regulators that directly serve large loads such as SoCs, while stepping it down to 12V to serve other needs. Google says its 48V approach has cut losses 16fold compared to 12V distribution.
Figure 1. Some designers are feeding 48V directly to PoL regulators in large systems such as data centres (Source: Intel FPGA)
There are reasons not to drive such high voltages so deep into the system architecture. A lot of infrastructure is already available to implement 12V distribution, such as silicon MOSFET switches and commodity regulators. On the other hand, single-stage 48V PoL regulators may need GaN switch transistors, which can be more expensive.
“It can come down to a question of capital expenditure versus operating expenditure,” said Mark Davidson, Intel PSG power division manager. “You may get more efficiency in really massive deployments with 48V PoLs, but stepping the high voltage down to 5 to 8V lets you use lower-cost PoLs.”
Distributing at lower voltage also gives ready access to specialist PoLs whose capabilities may be vital to meeting the complex needs of system-level chips.
The increasingly demanding IC
For decades, Moore’s Law brought us denser ICs that also consumed less power per unit area of die. Around the introduction of 90nm processes, power density stopped scaling with shrinking transistor dimensions and complex power-management strategies became necessary to stop ICs overheating. These include clock scaling, to slow a chip down if it is running too hot; voltage scaling, to address static power consumption; and power gating to reduce or turn off the power to functional blocks when they aren’t in use.
These strategies makes sense in theory, but in practice issues such as predicting future workloads and managing the latency of power-gating techniques make it challenging to implement them on complex ICs. For example, freezing a block may mean isolating its surroundings, saving its state, altering its supply voltage and clock frequency and waiting for them to settle, and then, when the block is needed again, reinitializing it and reconnecting it to the system. Sequencing represents another challenge, to ensure that as blocks within the IC demand different voltages, the order and rates at which supplies ramp up and down are managed to avoid latch-up at the interfaces between blocks.
The demands on PoL regulators, therefore, are becoming increasingly complex. They must be able to respond promptly to detailed commands from the power manager, such as for specific voltage ramps, and deal with very rapid changes in load. According to Intel circuit researcher James Tschanz, “Aggressive power gating may suddenly take a rail from tens of watts to milliwatts.”
PoL regulators also need to be able to track current swings without exceeding their voltage error or noise specifications. Designers may need to switch dynamically between buck regulators, which are usually more efficient at high currents, and low-noise low-drop-out (LDO) regulators, which can be more efficient at low currents. Regulators may also need to provide higher voltages for programming non-volatile memories, and manage the huge inrush currents and complex sequencing requirements of FPGAs – all without violating the stringent noise requirements that protect the functioning of analog circuits and SRAM blocks.
The upshot of this conflicting set of demands is that a system-level chip may be surrounded by several PoL regulators, plus a microcontroller unit (MCU) or FPGA to manage how they work together to serve its needs. Making the power-management strategy work effectively in real-world situations is becoming so complex that some design teams are addressing the issue by simply installing big capacitors near the biggest chips on their boards.
Finding a fix
Everyone want a better solution and many are trying to find one.
One of the most ambitious approaches is to absorb all the PoLs into large chips. Tschanz points to Intel’s Fully Integrated Voltage Regulator program, which has put both switching and linear regulators on some CPU dice.
“We can put switching regulators near the blocks they are supplying, with the inductors integrated into the package,” said Tschanz. “And we can put LDOs right near the on-die memories and PLLs.”
The result is that customers only have to provide a 1.8V rail, and don’t have to understand the chip’s power-management machinations too deeply.
Regulator vendors are also doing their bit to address the issue by developing PoLs with multiple output voltages and digital interfaces to allow two-way communications with power controllers, paying more attention to transient behavior, and using higher switching frequencies to meet more stringent noise requirements.
Another innovative approach to the power-management issue comes from start-up AnDAPT. Kapil Shankar, CEO, says that when a design problem starts presenting too many uncertainties, the industry’s response is usually programmability.
“In this case, an MCU has not been a good answer,” Shankar argues. “Especially with several concurrent real-time tasks, an MCU can’t guarantee the deterministic latency today’s power management requires.” And sometimes, the things you need to change are in the design of the analog paths, so software alone can’t help.
AnDAPT’s answer is a field-programmable mixed-signal chip it calls an Adaptive Multi-Rail Power Platform, as shown in Figure 2.
Figure 2. The AnDAPT Power Platform provides building blocks for a complete PoL solution (Source: AnDAPT)
The AnDAPT architecture has two SRAM-programmable fabrics, one of which is a configurable fabric of analog signal paths, and the other of which is a conventional FPGA fabric. These are complemented by several types of configurable functions, such as power blocks, sensor blocks, compensator RAMs, and Timers.
AnDAPT provides templates to configure these blocks for specific functions, such as to configure a power block to be any of a variety of switching regulators, LDO regulators, current-protection circuits, or current-sensing DAC/comparators. A sensor block can be programmed to be an error digitizer, comparator, instrumentation amp, or reference DAC. Compensation RAMs can act as look-up tables for arithmetic functions programmed into the FPGA fabric, to implement transfer functions for digital control loops. The FPGA fabric can implement state machines for control, sequencing, and interface functions. The analog fabric provides analog interconnect.
The AnDAPT Power Platform is configured through a graphic user interface, and then the device you have designed can be characterized with an integrated simulation tool.
Not every design will need AnDAPT’s flexibility, but it may provide a useful tool to help address the complexities of developing multi-level power distribution strategies for complex systems, boards and ICs.
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About the author
Ron Wilson is editor-in-chief of the System Design Journal publication from Altera which is now part of Intel. He has close to 40 years of experience in the electronics industry , and prior to joining Altera has held a variety of editorial positions with EE Times, serving as both editorial director and publisher of ISD Magazine and has written and edited for EDN Magazine, Computer Design, and Embedded Systems Design. Wilson holds a B.S. in Applied Science from Portland State University.
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