23 Apr 2010

Greg Martin, Product Marketing Manager, Achronix Semiconductor, explains how new FPGA architectures bring impressive performance improvements.

CEs can be initialized with a Data Token, or without. Wherever a register existed in the original design, they will have an initial Data Token, all other CEs will not have initial Tokens. The main difference between a series of uninitialized CEs and a wire, is that each pipeline stage between CEs is still capable of containing a Data Token, even if it doesn't start with one initially. This enables the throughput of Achronix FPGAs to be increased, while maintaining exact logical equivalence to a conventional circuit.

FEs have functionality equivalent to combinatorial logic. The only difference relates to how ingress and egress data is handled. The local handshaking within a picoPIPE network means the FEs must also handshake data in and out. This handshaking ensures only valid, settled data is evaluated and propagated.

BEs are only used at the boundary where the picoPIPE fabric meets the FPGA frame. These elements are responsible for converting Data Tokens in the frame into Data Tokens in the picoPIPE fabric (ingress). They are also used for converting Data Tokens in the fabric back into Data Tokens in the Frame (egress). Therefore every signal entering and exiting the picoPIPE fabric will pass through Ingress Boundary Elements and Egress Boundary Elements respectively.

Increased throughput

Higher throughput compared with existing FPGAs is achieved because of the fine-grained pipeline stages. Unlike existing FPGA implementations, these pipeline stages can be automatically inserted anywhere in a design without changing its logic functionality.

There are often many levels of logic between storage elements in traditional technology. It takes time for data to propagate from the Q register output, through the combinatorial logic and settle at a stable state on the next register's D input. As the clock cannot occur until all data is settled, the clock speed must run no faster than the longest path in the entire clock network. Data in every path that is shorter than the longest path (by definition, all paths except the longest) must wait for the longest path.

In contrast, picoPIPE technology allows optimum pipelining without changing the logic functionality. Each pipeline stage has less logic depth and therefore completes its operation very quickly. This allows the rate of Data Tokens through the logic to be increased, which increases the effective clock rate.

Achronix picoPIPE vs. Existing FPGA Implementation

In traditional FPGA, signals travel on long routing tracks and pass through many routing components. These signals suffer from a high capacitive load; and the larger the FPGA, the longer the paths that need to be traversed. Additionally, there are many levels of logic between state holding elements (registers).

Conventional Implementation vs. picoPIPE Implementation

Within Achronix FPGAs, the built in pipelining ensures that signals only ever need to travel on short routing tracks. This reduces the capacitance of the signal at each stage. For larger devices signals still may need to propagate from one corner of the device to the other. While larger devices may have slightly increased latency, unlike other FPGAs, they do not have decreased throughput, as each pipeline stage is capable of holding a new Data Token. Thus the inherent pipelining of picoPIPE technology allows maximum throughput to be maintained, regardless of how large the FPGA is. Pipelining also ensures there is only one logic level per pipeline stage, allowing a much faster rate of Data Tokens to be used.

Conclusion

Based on the patented picoPIPE technology, Achronix FPGAs can achieve a level of performance unobtainable with traditional FPGAs. Although the logic fabric is based on new technology, designers are not required to learn new design tools and techniques - making picoPIPE technology almost transparent to the designer. By mapping a design to picoPIPE technology, the design is automatically pipelined, without changing its behavior, significantly increasing the throughput that can be achieved. The innovative Achronix picoPIPE acceleration technology breaks through performance barriers and opens a new world of applications previously unavailable to FPGA designers.

Achronix is a registered trademark and Speedster is a trademark of Achronix Corp. All other brands, product names and marks are the property of their respective owners.

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