23 Apr 2010

Breaking through FPGA Performance Barriers

Greg Martin, Product Marketing Manager, Achronix Semiconductor, explains how new FPGA architectures bring impressive performance improvements.

Since their introduction in 1984, Field Programmable Gate Arrays (FPGAs) have given designers substantial flexibility and time-to-market advantages compared with ASICs. In recent years however, FPGAs have hit a wall.

FPGAs' great strength, reconfigurability, is unfortunately also the cause of a large weakness - low performance - keeping FPGAs from competing with ASICs despite smaller technology nodes being employed. As a result, traditional FPGAs have been prevented from playing a role in many high-performance systems where ASICs still dominate, even in low to medium volume applications where an FPGA would be a much more cost effective solution.

The economic and technical forces driving the high-performance electronics' world are leading to frustration with both the ASIC and traditional FPGA approaches. System architects increasingly require re-programmability and short time-to-market, while still satisfying their performance requirements.

This article demonstrates how an innovative new FPGA architecture with unprecedented capabilities is signalling a breakthrough in the nearly three decades of FPGA design where performance has often been sacrificed for flexibility and time-to-market. This new architecture blends elements of both synchronous and asynchronous architectures, delivering the world's first FPGAs capable of exceeding standard-cell ASIC performance. This breakthrough opens up worlds of applications previously unavailable to engineers using traditional FPGAs and will lead to more successful development programs producing more competitive products.

New FPGA Architecture

The revolutionary new FPGA architecture from Achronix can achieve three times the throughput of traditional FPGAs, approaching 1.5 GHz in peak performance. At the heart of this new architecture is the picoPIPE logic fabric - a fabric that is based on the use of Data Tokens rather than a conventional clocked structure. This high-performance fabric is surrounded by a conventional I/O frame of configurable I/Os, SerDes, clocks, PLLs etc. (Figure 1), providing the off-chip interfaces and forming the boundary between the picoPIPE core and these interfaces. All data entering and exiting the core must pass through the frame. From a designer's perspective, the internal picoPIPE fabric is virtually indistinguishable from a conventional FPGA fabric - the only distinction is that the data throughput is substantially increased.

Achronix FPGA Architecture

In conventional logic, a Data Token is a logic value which is qualified by a clock edge. With a traditional logic implementation, data is always present, but is only valid (and therefore propagated though storage elements) when a clock edge is received at a storage element. Hence every time data is propagated from one storage element to the next, only a distinct, valid data value is propagated. The combination of Clock and Data can therefore be implicitly considered as a Data Token. For each register (storage element) in a design, that has a clock , there will be a Data Token propagated at every clock tick.

In an Achronix FPGA, the picoPIPE fabric uses explicit Data Tokens, rather than implicit ones. Wherever there was an implicit data token in the original design, it will be replaced with an explicit Data Token once the design is mapped into the picoPIPE fabric. As explicit Data Tokens are used, the clock information is encoded into the Data Token - the fact that a token exists at all, indicates that a clock edge has occurred. As each Data Token contains both Data AND Clock information, no global clock is required within the fabric. Data Tokens are still clocked into and out of the Fabric using special elements in the Frame. The explicit Data Tokens are controlled by fast, local handshaking, rather than a global clock, hence are able to propagate at very high speeds.

The basic elements of a picoPIPE fabric are the Connection Element (CE), the Functional Element (FE), the Boundary Elements (BEs) and the pipeline stage. Pipeline stages connect CEs, FEs and BEs to form pipeline networks. Once combined into networks the picoPIPE implementation exactly matches the functionality of conventional FPGAs, but is capable of much higher throughput.

Achronix picoPIPE Building Blocks

Achronix picoPIPE Pipeline Stages

Each pipeline stage is capable of holding a Data Token, meaning that picoPIPE logic is highly pipelined by design. In traditional logic designs, adding pipeline stages will change the logic function computed. With picoPIPE logic this is not the case. picoPIPE pipeline stages can be added without automatically adding a new Data Token into the circuit. This is possible because the new data representation has separated pipeline stages from Data Tokens. In a traditional design, adding a pipeline stage (register) will always cause a new Data Token to also be introduced - and thus the functionality has been altered. picoPIPE logic has freed Data Tokens from being tied to pipeline stages, therefore pipeline stages can be added, without adding Data Tokens.

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