06 Oct 2016
Understanding & measuring jitter in electronic circuits
Andrea Dodini, European Marketing Manager, Keysight Technologies looks at how to identify the causes of jitter in electronic circuits and how to take steps to mitigate them.
Why are computers digital? Part of the answer is that converting the constantly varying signals that represent the world around us into binary digits makes it easier to preserve the information in those signals during subsequent processing than it would be when working directly with an analogue signal.
Although the 1s and 0s of a digital bit-stream can usually be easily distinguished from each other, those bits are still represented as electrical signals passing through a noisy analogue world. If enough electrical noise impinges on a digital signal, it can cause the binary waveform to ‘jitter’, or be offset in time.
This electronic circuit jitter can cause problems if the point at which a signal changes from 0 to 1 or 1 to 0 is shifted so far that its value is misinterpreted at the sampling point. When this happens, the receiving circuit may misinterpret the binary value of the waveform, introducing a transmission error.
Sources of jitter in electronic circuits
There are various types of jitter in electronic circuits, and understanding the characteristics of each type can help engineers identify their causes and take steps to mitigate them. The main causes of jitter are as follows:
These are effects on a signal that result from the characteristics of its being a digital system in an analogue environment. Examples of these system-related sources include crosstalk from radiated or conducted signals, dispersion effects and impedance mismatches.
These sources of jitter are due to the pattern of data being transferred and include inter-symbol interference, duty-cycle distortion and pseudorandom, bit sequence periodicity.
These jitter sources include:
kTB noise, which is associated with electron flow in conductors and increases with bandwidth, temperature, and noise resistance
Shot noise: electron and hole noise in semiconductors in which the magnitude is governed by bias current and measurement bandwidth
Pink noise: noise that is spectrally related to 1/f
Bounded and unbounded jitter
The sources of jitter in electronic circuits are often further categorised as ‘bounded’ or ‘unbounded’.
Bounded (or deterministic) jitter sources reach maximum and minimum phase deviation values within an identifiable time interval. This type of jitter is due to systematic and data-dependent phenomena, as identified in the first and second groups above.
Unbounded (or random) jitter sources do not achieve a maximum or minimum phase deviation within any time interval, and the jitter amplitude from these sources can approach infinity (in theory).
The total jitter on a signal, specified as a phase-error function, is the sum of the deterministic and random jitter components affecting the signal.
The deterministic jitter component is determined by adding the maximum phase (or time) advance and phase (or time) delay produced by the deterministic (bounded) jitter sources.
The random jitter component is the aggregate of all the random noise sources affecting the signal. Random jitter is assumed to follow a Gaussian distribution and is defined by the mean and sigma of that Gaussian distribution.
Jitter eye diagrams
An eye diagram superimposes all the bit periods of a captured waveform, as shown in idealised form in Figure 1.
Figure 1: An idealised eye diagram (Source: Keysight Technologies)
This eye diagram has very smooth and symmetrical transitions at the left and right crossing points. A large, wide-open ‘eye’ in the centre shows the ideal location (‘x’) for sampling each bit. At this sample point the waveform should have settled to its high or low value and, if sampled here, is least likely to result in a bit error.
Figure 2 shows a more realistic eye diagram, which shape provides a lot of information about the signal without having to resort to more complex measurements.
Figure 2: An eye diagram with an irregular shape provides a wealth of information (Source: Keysight Technologies)
For example, the bottom of the waveform has a smaller variation in amplitude than the top, so the signal seems to carry more 0s than 1s. There are four different trajectories in the bottom, so at least four 0s in a row are possible. At the top of the waveform, there are, at most, two trajectories, so the waveform can only contain up to two 1s in a row. The waveform has two different rising and falling edges, showing that it is subject to deterministic jitter. Finally, the rising edges have a greater spread than the falling edges, and some of the crossover points intersect below the threshold level, showing that duty cycles are being distorted causing 0s to have a longer On time than 1s.
Other ways to view jitter
There are multiple ways of visualising jitter, and if several of them are applied to the same signal it can help identify the sources of jitter and so indicate ways to reduce it.
A histogram plots the range of values exhibited by a chosen parameter (often time or magnitude) along the x-axis versus the frequency of occurrence on the y axis.
In jitter analysis, histograms can be used to plot waveform parameters such as rise time, fall time, period, or duty cycle, to reveal conditions such as multi modal performance distributions that can then be correlated with circuit conditions such as transmitted patterns. Histograms can also be used to provide essential data sets for the jitter separation routines required by various digital bus standards.
Figure 3: Histogram of period jitter (Source: Keysight Technologies)
The histogram in Figure 3 shows period jitter in a clock signal. The left hump of the histogram appears to have a normal Gaussian shape but the right side has two peaks, suggesting that the signal includes second and fourth harmonics that are causing jitter.
The bathtub plot
The bathtub plot shown in Figure 4 graphs the bit error rate (BER) of a signal versus its sampling point, using a horizontal scale that represents the time it takes for a single symbol to be transmitted. BER is represented on a log scale, to show the relationship between it and the sampling point.
Figure 4: Bathtub plot (Source: Keysight Technologies)
When the sampling point is at or near the transition points, the BER is 0.5, so it is equally likely that the transmission of a bit will succeed or fail. The curve is fairly flat in these regions, which are dominated by deterministic jitter. As the sampling point moves away from the transition point, the BER drops off rapidly. These regions are dominated by random jitter processes so the BER is determined by the sum of the jitter produced by these processes. The bathtub plot shows that the best time to sample the signal, with the lowest BER, is halfway between the beginning and end of the symbol transmission time.
In the frequency domain
Another way of analysing jitter is to consider the frequency distribution of phase noise or jitter spectra. This can reveal deterministic jitter sources because they appear as line spectra. This kind of visualisation can also reveal phase noise or jitter-versus-frequency offsets from a carrier or clock.
Phase-noise measurements can provide useful insights into phase-locked-loop or crystal-oscillator designs, and help identify deterministic jitter due to spurious signals. Such measurements are useful for optimising clock-recovery circuits and discovering any internal sources of spurs and noise.
Figure 5 shows the intrinsic jitter spectrum of a phase-locked loop. The noise peaks at a 2 kHz offset. There are also lines that identify deterministic jitter sources at frequencies from 60 Hz to approximately 800 Hz, indicating that they are spurious signals generated by the power lines. Frequency lines are also evident from 2 to 7 MHz, and are most likely to be spurious signals derived from the reference clock, causing deterministic jitter.
Figure 5: Intrinsic jitter spectrum (Source: Keysight Technologies)
Another method of obtaining a frequency-domain viewpoint of jitter is to take a fast Fourier transform (FFT) of the time interval error data, which is defined as the phase difference between the signal being measured and the reference clock. The FFT has much less resolution than the low-level phase-noise view, but is good at revealing high-level phenomena quickly and easily.
Resolving jitter in electronic circuits is an essential part of product development. Bounded or deterministic jitter can arise from the system or be data-dependent.
Unbounded jitter is attributed to random noise. To analyse the collective impact of these jitter types, a combination of jitter measurement approaches such as eye diagrams, histograms, bathtub plots and time-domain frequency can provide useful insights.
Once engineers have identified and understood the sources of jitter in their electronic designs, they are should be in a much better position to find ways to reduce or eliminate it, hence improving the transmission performance of their designs.
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About the author
Andrea Dodini is Marketing Manager at Keysight Technologies for Small and Middle Size Enterprises (SME) and for Keysight Core Product Lines in Europe, the Middle East, Africa and India (EMEAI).
Keysight echnologies Inc. is the world's leading electronic measurement company, transforming today's measurement experience through innovations in wireless, modular, and software solutions. With its HP and Agilent legacy, Keysight delivers solutions in wireless communications, aerospace and defence and semiconductor markets with world-class platforms, software and consistent measurement science. Keysight's singular focus on measurement helps scientists, researchers and engineers address their toughest challenges with precision and confidence. With the help of their products and services, they are better able to deliver the breakthroughs that make a measurable difference.
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