Integrated PLLs and VCOs for Wireless Applications

Ian Collins, Applications Engineer, RF Group, Analog Devices, Inc. explains how to design PLLs and VCOs using integrated circuit chips.

This article on Integrated PLLs and VCOs for Wireless APplications is split into two parts:

Integrated Phase Locked Loops and Voltage Controlled Oscillator (VCO) integrated circuits (IC's) are now commonplace, and have been adopted for use in many wireless standards offering wider frequency range, flexibility and features compared to stand alone VCO's. This article outlines some of the technical challenges posed by integrated PLL & VCO parts in wireless applications, and how to solve them.

The past decade has seen huge advances in the development of PLLs with integrated circuits. These advances have generally simplified design of Local Oscillator (LO) and clocking circuits, with a reduction in component count, wider frequency range and greater flexibility.

Some properties of integrated PLL & integrated VCO devices present new challenges to the RF engineer. With reference to the Analog Devices part, the ADF4350, we will take a more detailed look at these.

Multi-band VCO's

Stand-alone VCO's tend to have limited frequency ranges of 100 MHz or less. By contrast, the ADF4350 covers a frequency range from 137.5 - 4400 MHz by use of a multi-band VCO operating between 2.2 - 4.4 GHz, together with output dividers to realize lower frequencies. Generally speaking, low VCO phase noise is dependent on high VCO tank circuit Q. A high VCO circuit Q implies small frequency range and sensitivity (Kv) of the VCO, a fundamental trade-off in VCO design. Many octave tuning VCO's solve this issue by extending the tuning voltage (VTUNE) to as high as 30 Volts, permitting a reduction in VCO sensitivity. But the ADF4350 solves this problem by dividing the frequency range into three separate VCO's, with sixteen VCO sub-bands in each VCO as shown below.

ADF4350 Frequency vs. V_TUNE

This necessitates a method of choosing the correct VCO band for each frequency update. Rather than use a look up table, which will not allow for manufacturing variations in band transitions, a VCO band select circuit is used which examines the output from the reference (R) and feedback (N) counters, and chooses the most appropriate VCO and sub-band for the programmed output frequency. This process necessitates a switching time, during which the open loop output frequency can be at a variety of different frequencies. This band select switching time is also added to the PLL lock time, which itself is a function of the PLL loop filter bandwidth. The ADF4350 contains a separate RF output stage after the VCO, which can be muted during the band select and PLL lock time, until the PLL lock detect asserts lock, and the output stage is automatically turned on. This mute till lock detect feature can be used to prevent any unwanted LO frequencies being generated during lock time and band select.

Power supplies

VCO pushing is measured by applying a steady dc tuning voltage to the ADF4350 VTUNE pin, varying the power supply voltage, and measuring the frequency change. The pushing figure (P) equals the frequency delta divided by the voltage delta, as shown in the table below.

In a PLL system, higher VCO pushing means that power supply noise will degrade the VCO phase noise. If VCO pushing is low, then power supply noise will not significantly degrade phase noise. However, for high VCO pushing, noisy power supplies will have a measurable impact on phase noise performance.

Experiments showed pushing to be at its maximum at 4.4 GHz VCO output frequency, so the comparison of VCO performance with different regulators was made at this frequency. Rev. A evaluation boards of the ADF4350 used the ADP3334 LDO regulator. The integrated rms noise of this regulator is 27 µV (integrated from 10 Hz to 100 kHz). This compares to 9 µV for the ADP150, which is used on the EVAL-ADF4350EB1Z, Rev B. In order to measure the impact of the power supply noise, a narrow PLL loop bandwidth (10 kHz) was used to facilitate greater examination of VCO phase noise.

A more detailed examination of the output noise density with frequency is available from the data sheets of both the ADP3334 and ADP150. The noise spectral density of the ADP3334 regulator is 150 nV/√Hz at 100 kHz offset. The same figure for the ADP150 shows 25 nV/√Hz.

Where L_(LDO) is the noise contribution from the regulator to the VCO phase noise (in dBc/Hz), at an offset fm; P is the VCO pushing figure in Hz/V; Sfm is the noise spectral density at a given frequency offset in V/√Hz; and fm is the frequency offset at which the noise spectral density is measured in Hz.

ADF4350 Phase Noise at 4.4 GHz with ADP3334 Regulators

ADF4350 Phase Noise at 4.4 GHz with ADP150 Regulators

The noise contribution from the supply is then rss summed with the noise contribution of the VCO (itself measured with a very low noise supply) to give the total noise at the VCO output with a given regulator.

These noise performances are rss summed together to give the expected VCO phase noise:

Or expressed in dB:

In this example, a 100 kHz noise spectral density offset is chosen, a 6 MHz/V pushing figure is used, and ?110 dBc/Hz is taken as the VCO noise with an ideal supply.

Using a dedicated signal source analyzer (like Rohde & Schwarz FSUP), the VCO phase noise is compared. At 100 kHz offset the ADP3334 delivers ?102.6 dBc/Hz, and in the same configuration the ADP150 measures ?108.5 dBc/Hz. The integrated phase noise improves from 1.95° to 1.4° rms also. The measured results correlate very closely with the calculations and clearly show the benefit of using the ADP150 with the ADF4350. This underlines the importance of using low noise regulators for the VCO circuit of the ADF4350. A more detailed summary of the experiment is contained in CFTL-0147 (Circuit from the Lab 0147, on www.analog.com).

Further pages from this tutorial
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