Integrated PLLs and VCOs [Part 2]

This article on Integrated PLLs and VCOs for Wireless APplications is split into two parts:

The first part of this article about integrated circuit PLLS and VCOs looked at multiband VCOs and the noise introduced by regulators.

This second part of the article now turns to look at the important topic of loop filter design and the way this affects everything in the loop from its response to the phase noise performance.

The article also looks at the use of these chips with external PLLs and up down converters.

Loop Filter Design

On integer-N PLL's, the phase noise at offsets close to the carrier is dominated by the contribution from the PLL synthesizer. This is particularly the case with narrow-band systems like GSM which require 200 kHz spacing. The ADF4350 contains a fractional-N PLL which greatly reduces in-band noise compared to integer-N (See Analog Dialogue volume 36, Ask the Applications Engineer, PLL's. for more detail).

Using an integer-N PLL like the ADF4106, the in-band noise at 5 kHz offset (calculated from ADIsimPLL) is -95 dBc/Hz. Examining a suitable VCO for the application, the RFMD VCO 915-191U, the open-loop VCO phase noise at 5 kHz offset is -101 dBc/Hz, so in this case a smaller loop bandwidth than 5 kHz would permit lower rms phase error (or transit EVM). However, most integer-N PLL's for GSM applications are designed with 10-20 kHz loop filters, because a smaller loop filter will lead to a larger PLL lock time.

VCO-191-915U Open loop phase noise

ADF4350 Open loop VCO phase noise

On the ADF4350, the open loop VCO phase noise tends to be comparable to the discrete VCO at offsets of 1 MHz or greater (-145 dBc/Hz), but at 5 kHz offset, the ADF4350 open loop VCO noise (for 915 MHz) is -81 dBc/Hz. However, because the ADF4350 contains a fractional-N PLL, the in-band noise contribution (from the PLL) at this same offset is -105 dBc/Hz. Since the PLL noise is lower than the VCO noise at the same offset it makes sense to increase the loop bandwidth to ~40 kHz, minimizing the rms phase error. This results in a 3x improvement in rms phase error compared to the Integer-N configuration (two graphs below). One can conclude from this experiment that it makes sense to use high PFD frequencies with loop filter bandwidths between 20 - 40 kHz on the ADF4350.

ADF4106 & external VCO, rms error 0.3°

ADF4350, rms error 0.1°

Another aspect of the ADF4350 loop filter design is the variation of the VCO sensitivity (Kv). The variation between the minimum Kv (18 MHz/V) to the maximum (58 MHz/V) can be a factor of 3x. Sensitivity varies in each VCO band (peaking in the middle of a band), and generally increases between bands as the frequency increases. Because of the large difference in Kv values, the geometric mean of VCO sensitivity is the most suitable value for PLL loop filter design. The graph of sensitivity below (Figure 8) shows two traces. The first (in bold) is the absolute sensitivity against frequency, and the second is the geometric mean of sensitivity for each VCO band, with a trend line added to give the geometric mean for each VCO band. The geometric mean of these sensitivities is approximately 33 MHz/V, which is close to the geometric mean of the two extremes of sensitivity listed above.

The implication is that for a given loop filter design, the geometric mean of the sensitivity for the maximum and minimum VCO frequency should be chosen. In practice, many applications will use the lowest and highest VCO frequencies (2.2 and 4.4 GHz), and in this case 33 MHz/V is recommended. In cases where a smaller subset of VCO frequencies is used then a more specific value of Kv is recommended. For example, if VCO frequencies 4.0 and 4.4 GHz are used, then, from the graph below, the geometric mean of 40 MHz/V (for 4.0 GHz) and 48 MHz/V (for 4.4 GHz) is 43 MHz/V. All of the above procedures are automatically followed in ADIsimPLL, and it is strongly recommended for low pass filter designs for the ADF4350.

ADF4350 with external PLL

Some applications may necessitate the use of an external PLL. These can include spur critical applications, or applications requiring sub-Hz resolution on the RF output. The ADF4350 contains a fractional-N PLL which is fabricated on the same die as the VCO. One effect of this is that spurs generated by the Reference (R) and Feedback (N) counters, the Phase Frequency Detector (PFD), and the sigma-delta could all easily couple to the VCO. Using an external PLL (ADF4153, ADF4156, ADF4157, ADF4150), and disabling the internal PLL can improve these spurs.

For applications requiring greater resolution at the RF output, a PLL such as the ADF4157 offers 25-bit modulus resolution, meaning that the Fractional part of the N divider, used with a 10 MHz PFD frequency, can generate frequency steps as small as 0.3 Hz. By contrast, the ADF4350 PLL contains a programmable 12 bit modulus (highest value 4095), which in a similar configuration to that above provides 2.5 kHz frequency resolution. Users wishing to achieve higher resolution can use the external PLL instead of the internal one.

VCO band select is still necessary and performed by the internal PLL, which can then be disabled after band select by holding the ADF4350 internal counters in reset (the counter reset feature). The spurious performance is improved by the greater isolation of the PLL circuitry from the VCO. The basic hardware connection is detailed below.

Use with Up/Down Converters

To achieve lower frequencies than 2200 MHz, it is necessary to use the output dividers on the ADF4350. Due to the architecture of the dividers, the output spectrum contains more harmonics, and at lower frequencies can resemble a square wave. If the part is to be used as the LO to a modulator or demodulator (mod's/demod's), it can be important to prototype the ADF4350 with the conversion stage to check the behaviour of the modulated/demodulated output.

On some mod/demods like the ADL5385, a divide by two stage exists after the LO input to the modulator, and the harmonic content of the LO is irrelevant as the necessary quadrature for up-conversion is generated by the divide by two circuit on the modulator. But, on some modulators like the ADL5375, the quadrature necessary for up-conversion is generated by a poly-phase filter, which can be sensitive to LO harmonic levels. High LO harmonics can degrade sideband suppression. In cases such as this, filtering of the harmonic levels is necessary to achieve the expected sideband performance. Figure For more information on this the circuit note CFTL-0134 contains more of the necessary detail.

Sideband Suppression for Filter b, 850 MHz to 2450 MHz

Ian Collins is an applications engineer for the RF Group at Analog Devices, Inc. He is responsible for both RF and microwave devices testing and development. He can be reached via email at ian.collins@analog.com.

Analog Devices Inc is a leader in high performance signal processing solutions. The company ICs for data converters, amplifiers, DSP, RF & communications, power and thermal management, supervisory and interface, and MEMs. Develops analog, digital, linear, and mixed-signal integrated circuits including data converters, amplifiers, DSP, RF, and more.

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